Abstract: A manufacturing method is provided for a power semiconductor device that enables reducing its on-state voltage and power loss. The semiconductor device includes a set of L-shaped trench gates 3 each formed, from the top-side surface of a p base layer 2, perpendicularly with respect to a first main surface of an n? layer 1, to reach into a location of the n? layer 1. At the lower ends of each of the trench gates 3, bottom portions 3d are provided to unilaterally extend a predetermined length in one direction parallel to the first main surface of the n? layer 1. In addition, the extending end of one of the bottom portions 3d opposes that of the other bottom portion, on the extending side of the bottom portions 3d, and the interspace between each pair of adjacent bottom portions 3d is set narrower than any other interspace between the trench-gate parts that are perpendicularly formed with respect to the first main surface of the n? layer 1.

Abstract: A manufacturing method is provided for a power semiconductor device that enables reducing its on-state voltage and power loss. The semiconductor device includes a set of L-shaped trench gates 3 each formed, from the top-side surface of a p base layer 2, perpendicularly with respect to a first main surface of an n? layer 1, to reach into a location of the n? layer 1. At the lower ends of each of the trench gates 3, bottom portions 3d are provided to unilaterally extend a predetermined length in one direction parallel to the first main surface of the n? layer 1. In addition, the extending end of one of the bottom portions 3d opposes that of the other bottom portion, on the extending side of the bottom portions 3d, and the interspace between each pair of adjacent bottom portions 3d is set narrower than any other interspace between the trench-gate parts that are perpendicularly formed with respect to the first main surface of the n? layer 1.

Abstract: A semiconductor device which includes a set of trench gates each formed, from the top-side surface of a p base layer, perpendicularly with respect to a first main surface of an p-layer, to reach into a location of the n-layer. At the lower ends of each of the trench gates, bottom portions are provided to unilaterally extend a predetermined length in one direction parallel to the first main surface of the n-layer. In addition, the extending end of one of the bottom portions opposes that of the other bottom portion, on the extending side of the bottom portions, and the distance between each pair of adjacent bottom portions is set narrower than any other distance between the trench-gate parts that are perpendicularly formed with respect to the first main surface of the n-layer.

Abstract: A power semiconductor device and its manufacturing method are provided that enable reducing its on-state voltage and power loss. The semiconductor device includes a set of L-shaped trench gates 3 each formed, from the top-side surface of a p base layer 2, perpendicularly with respect to a first main surface of an n? layer 1, to reach into a location of the n? layer 1. At the lower ends of each of the trench gates 3, bottom portions 3d are provided to unilaterally extend a predetermined length in one direction parallel to the first main surface of the n? layer 1. In addition, the extending end of one of the bottom portions 3d opposes that of the other bottom portion, on the extending side of the bottom portions 3d, and the interspace between each pair of adjacent bottom portions 3d is set narrower than any other interspace between the trench-gate parts that are perpendicularly formed with respect to the first main surface of the n? layer 1.