Patents by Inventor Hirofumi Shibuya
Hirofumi Shibuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
Patent number: 9904619Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: GrantFiled: April 2, 2014Date of Patent: February 27, 2018Assignee: Emergence Memory Solutions, Inc.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura -
Publication number: 20140365712Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: ApplicationFiled: April 2, 2014Publication date: December 11, 2014Applicant: SOLID STATE STORAGE SOLUTIONS LLCInventors: Shigemasa SHIOTA, Hiroyuki GOTO, Hirofumi SHIBUYA, Fumio HARA, Yasuhiro NAKAMURA
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Publication number: 20120176842Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: ApplicationFiled: October 10, 2011Publication date: July 12, 2012Inventors: SHIGEMASA SHIOTA, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Patent number: 8219882Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.Type: GrantFiled: May 21, 2008Date of Patent: July 10, 2012Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
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Patent number: 8103899Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.Type: GrantFiled: October 3, 2008Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Patent number: 8042021Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.Type: GrantFiled: April 18, 2011Date of Patent: October 18, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
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Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
Patent number: 8036040Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: GrantFiled: October 14, 2008Date of Patent: October 11, 2011Assignee: Solid State Storage Solutions LLCInventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura -
Publication number: 20110197108Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
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Patent number: 7954039Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.Type: GrantFiled: September 25, 2007Date of Patent: May 31, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
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Patent number: 7752526Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.Type: GrantFiled: May 14, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Publication number: 20100054069Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: ApplicationFiled: October 14, 2008Publication date: March 4, 2010Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Patent number: 7596041Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.Type: GrantFiled: October 3, 2007Date of Patent: September 29, 2009Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
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Patent number: 7552311Abstract: The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.Type: GrantFiled: February 27, 2007Date of Patent: June 23, 2009Assignee: Renesas Technology Corp.Inventors: Fumio Hara, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya
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Publication number: 20090037767Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.Type: ApplicationFiled: October 3, 2008Publication date: February 5, 2009Inventors: SHIGEMASA SHIOTA, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Patent number: 7475165Abstract: Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.Type: GrantFiled: February 16, 2005Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Kinji Mitani, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
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Patent number: 7450457Abstract: A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: GrantFiled: April 16, 2007Date of Patent: November 11, 2008Assignee: Solid State Storage Solutions LLCInventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Patent number: 7447936Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.Type: GrantFiled: October 19, 2006Date of Patent: November 4, 2008Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Publication number: 20080229164Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.Type: ApplicationFiled: May 21, 2008Publication date: September 18, 2008Inventors: Takayuki TAMURA, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
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Patent number: 7392457Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.Type: GrantFiled: July 14, 2005Date of Patent: June 24, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
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Publication number: 20080137452Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.Type: ApplicationFiled: October 3, 2007Publication date: June 12, 2008Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara