Patents by Inventor Hirofumi Shinoda

Hirofumi Shinoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11983967
    Abstract: A control apparatus (2000) computes a waiting time index value for each of a plurality of gates (20) for entering an area (10). The control apparatus (2000) detects, from among the plurality of gates (20), a first gate (20) and a second gate (20) of which relation between the waiting time index values satisfies a first criterion. Herein, the waiting time index value of the first gate (20) is greater than the waiting time index value of the second gate (20). The control apparatus (2000) causes a terminal (30) associated with the first gate (20) to output priority use information, which allows prioritized use of the second gate (20).
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 14, 2024
    Assignee: NEC CORPORATION
    Inventors: Hirofumi Inoue, Shin Tominaga, Shigeki Shinoda, Yuzo Senda, Shigeru Sekine
  • Publication number: 20100090323
    Abstract: The present invention provides a spacer sheet for a complex type semiconductor device provided between the semiconductor packages of a complex type semiconductor device formed by laminating plural semiconductor packages, comprising through holes of an array corresponding to electrodes which can be provided onto a substrate of one semiconductor package and which are formed in order to connect and wire one semiconductor package with the other semiconductor package and a space part corresponding to a principal part of the above one semiconductor package mounted on the substrate or a principal part of the other semiconductor package opposed to the substrate and a production process for a complex type semiconductor device in which the above spacer sheet is used.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 15, 2010
    Applicant: Lintec Corporation
    Inventors: Tomonori Shinoda, Hironori Shizuhata, Hirofumi Shinoda, Yuji Kawamata, Takeshi Tashima, Masato Shimamura, Masako Watanabe, Masazumi Amagai
  • Publication number: 20100025837
    Abstract: The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on a lower surface in the upper semiconductor package and a principal part of the upper semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively upper part, a lower semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on an upper surface in the lower semiconductor package and a principal part of the lower semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively lower part, a spacer sheet which comprises a space part corresponding to the principal part of the upper semiconductor package and/or the principal part of th
    Type: Application
    Filed: October 22, 2007
    Publication date: February 4, 2010
    Applicant: LINTEC CORPORATION
    Inventors: Tomonori Shinoda, Hironori Shizuhata, Hirofumi Shinoda, Yuji Kawamata, Takeshi Tashima, Masato Shimamura, Masako Watanabe, Masazumi Amagai