Abstract: There is provided a data re-synchronization apparatus for suppressing occurrence of a jitter in a high-speed serial signal transmitted over a long distance to improve a reliability of re-synchronized data. In the apparatus, a shift register serial-parallel conversion circuit inputs the serial signal ant converts an input data signal to parallel data signals of a predetermined number of parallel bits. An input data extension circuits extend the parallel data signals by a predetermined clock length time-axially to provide extended data signals. An input pattern detection circuit sends an input take-in signal so that data can be taken in at roughly a center of variation points of the extended data signals, while a re-synchronized data take-in signal generation circuit latches the input take-in signal in synchronization with an output clock signal.

Abstract: There is provided a data re-synchronization apparatus for suppressing occurrence of a jitter in a high-speed serial signal transmitted over a long distance to improve a reliability of re-synchronized data. In the apparatus, a shift register serial-parallel conversion circuit inputs the serial signal ant converts an input data signal to parallel data signals of a predetermined number of parallel bits. An input data extension circuits extend the parallel data signals by a predetermined clock length time-axially to provide extended data signals. An input pattern detection circuit sends an input take-in signal so that data can be taken in at roughly a center of variation points of the extended data signals, while a re-synchronized data take-in signal generation circuit latches the input take-in signal in synchronization with an output clock signal.

Abstract: A data check device of a magnetic disk device including a controller side data check circuit for conducting, at data writing, generation of an ECC for data sent from an upper circuit, sending of data through a data signal line and, in synchronism, sending of the ECC onto a parity signal line, and at data reading, reception of data on the data signal line, reception of an ECC on the parity signal line, an ECC check based on the data and the ECC, correction of an error when the error is detected in the ECC check. Comparable data checking is performed on the drive side which includes a lower circuit.

Abstract: In order to bring and keep a slave phase of rotation of a slave spindle into and in synchronism with a master phase, the master phase is represented in a predetermined time duration by zeroth through (N-1)-th master region data with an N-th master region datum added, where N represents a predetermined integer which is not less than two. The slave phase is represented, during one rotation of the slave spindle, by zeroth through (N-1)-th slave region data with an N-th slave region datum additionally used to provide a guard time. The zeroth through the (N-1)-th slave and master region data are compared to render a phase difference between the master and the slave phases either to zero or to a predetermined value. Alternatively, the master phase is represented in the predetermined time duration by a sequence of composite pulses which comprise N master clock pulses with at least one of the clock pulses omitted to indicate a start point of the sequence.

Abstract: In order to bring and keep a slave phase of rotation of a slave spindle into and in synchronism with a master phase, the master phase is represented in a predetermined time duration by zeroth through (N-1)-th master region data with an N-th master region datum added, where N represents a predetermined integer which is not less than two. The slave phase is represented, during one rotation of the slave spindle, by zeroth through (N-1)-th slave region data with an N-th slave region datum additionally used to provide a guard time. The zeroth through the (N-1)-th slave and master region data are compared to render a phase difference between the master and the slave phases either to zero or to a predetermined value. Alternatively, the master phase is represented in the predetermined time duration by a sequence of composite pulses which comprise N master clock pulses with at least one of the clock pulses omitted to indicate a start point of the sequence.