Patents by Inventor Hirofumi Watani

Hirofumi Watani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a multilayer interconnection structure and fabrication method thereof
    Patent number: 7416985
    Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Tamotsu Yamamoto, Hirofumi Watani, Hideki Kitada, Hiroshi Horiuchi, Motoshu Miyajima
  • Semiconductor device having a multilayer interconnection structure and fabrication method thereof
    Publication number: 20050212137
    Abstract: A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench formed in the first interlayer insulation film and having a sidewall surface and a bottom surface covered with a first barrier metal film, a via-hole formed in the second interlayer insulation film and having a sidewall surface and a bottom surface covered with a second barrier metal film, an interconnection pattern filling the interconnection trench, and a via-plug filling the via-hole, wherein the via-plug makes a contact with a surface of the interconnection pattern, the interconnection pattern has projections and depressions on the surface, the interconnection pattern containing therein oxygen atoms along a crystal grain boundary extending from the surface toward an interior of the interconnection pattern with a concentration higher than a concentration at the surface.
    Type: Application
    Filed: January 26, 2005
    Publication date: September 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Tamotsu Yamamoto, Hirofumi Watani, Hideki Kitada, Hiroshi Horiuchi, Motoshu Miyajima