Abstract: A video input interface receives video data on which a known character is to be drawn. A memory stores reference graphic data describing the known character. A visibility detector checks the visibility of the known character drawn on the video data based on the reference graphic data.

Abstract: A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads, and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.

Abstract: A video input interface receives video data. An OSD circuit draws an intermediate layer in a target region in which an OSD character is to be overlaid on the video data, and overlays the OSD character on the intermediate layer.

Abstract: A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.

Abstract: A video input interface of a semiconductor apparatus receives a digital video signal. A decoder extracts a packet command mapped in an RGB data format to a blind area that is included within an active area of the digital video signal and that is not to be displayed on a display panel, and decodes the packet command. A processing unit executes processing according to the packet command.

Abstract: In a normal state, a video input interface receives video data. In a setup state, a control input interface receives multiple items of compressed image data, and stores the compressed image data in memory. In the normal state, a decoder reads one item from among the multiple items of compressed image data from the memory according to an instruction signal that indicates graphics data to be displayed, and decodes the compressed image data thus read so as to reproduce the original graphics data before compression. A multiplexer superimposes the graphics data on the video data.

Abstract: In a normal state, a video input interface receives video data. In a setup state, a control input interface receives graphics data for an On Screen Display (OSD) function. In the setup state, an encoder encodes the graphics data, and stores compressed image data S6 thus encoded in memory. In the normal state, a decoder reads one item of the compressed image data from the memory according to an instruction signal, and decodes the compressed image data thus read so as to reproduce the original graphics data. A multiplexer superimposes graphics data on frame data, and outputs the superimposed graphics data.

Abstract: A video input interface receives video data. An OSD circuit draws an on screen display (OSD) character on the video data. The visibility detector checks whether the visibility of the OSD character is good or poor. A determination criterion for the visibility dynamically changes in a manner that depends on a background of the OSD character.

Abstract: A video input interface receives video data on which a known character is to be drawn. A memory stores reference graphic data describing the known character. A visibility detector checks the visibility of the known character drawn on the video data based on the reference graphic data.

Abstract: A video input interface receives video data. An OSD circuit draws an intermediate layer in a target region in which an OSD character is to be overlaid on the video data, and overlays the OSD character on the intermediate layer.

Abstract: There is provided an in-vehicle timing controller, which includes a main input interface configured to receive input image data from an image processor, an input pin configured to receive a vehicle signal indicating a state of a vehicle from the vehicle, a sub image generator configured to generate sub image data based on the vehicle signal, and an image processing circuit configured to generate output image data to be displayed on a display panel based on at least one of the input image data and the sub image data.

Abstract: A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.

Abstract: In a normal state, a video input interface receives video data. In a setup state, a control input interface receives graphics data for an On Screen Display (OSD) function. In the setup state, an encoder encodes the graphics data, and stores compressed image data S6 thus encoded in memory. In the normal state, a decoder reads one item of the compressed image data from the memory according to an instruction signal, and decodes the compressed image data thus read so as to reproduce the original graphics data. A multiplexer superimposes graphics data on frame data, and outputs the superimposed graphics data.

Abstract: In a normal state, a video input interface receives video data. In a setup state, a control input interface receives multiple items of compressed image data, and stores the compressed image data in memory. In the normal state, a decoder reads one item from among the multiple items of compressed image data from the memory according to an instruction signal that indicates graphics data to be displayed, and decodes the compressed image data thus read so as to reproduce the original graphics data before compression. A multiplexer superimposes the graphics data on the video data.

Abstract: A video input interface of a semiconductor apparatus receives a digital video signal. A decoder extracts a packet command mapped in an RGB data format to a blind area that is included within an active area of the digital video signal and that is not to be displayed on a display panel, and decodes the packet command. A processing unit executes processing according to the packet command.

Abstract: A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.

Abstract: A main input interface receives input image data. Memory stores multiple segment data that specify the on/off states of the multiple respective segments that form a segment character on an image frame. A sub input interface receives sub data that specifies the segment character to be displayed. A segment decoder converts the segment character into a raster image based on the sub data and the multiple segment data. An image processing circuit generates output image data to be displayed on a display panel, based on at least one of the input image data and the output data of the segment decoder.

Abstract: There is provided an in-vehicle timing controller, which includes a main input interface configured to receive input image data from an image processor, an input pin configured to receive a vehicle signal indicating a state of a vehicle from the vehicle, a sub image generator configured to generate sub image data based on the vehicle signal, and an image processing circuit configured to generate output image data to be displayed on a display panel based on at least one of the input image data and the sub image data.

Abstract: A main input interface receives input image data. Memory stores multiple segment data that specify the on/off states of the multiple respective segments that form a segment character on an image frame. A sub input interface receives sub data that specifies the segment character to be displayed. A segment decoder converts the segment character into a raster image based on the sub data and the multiple segment data. An image processing circuit generates output image data to be displayed on a display panel, based on at least one of the input image data and the output data of the segment decoder.