Patents by Inventor Hirohide Komiyama
Hirohide Komiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080238788Abstract: An apparatus has an antenna distance setting mechanism that sets a distance between a cosmetic cover and a radio antenna. An upper housing and a radio antenna, which has a ground and a radiating element and is movably attached to the upper housing, are covered by a cosmetic cover formed of a dielectric material. An antenna distance setting mechanism includes a radio antenna supporting member, elastic members, and protrusions. The radio antenna-supporting member is movably attached to the upper housing. When the cosmetic cover is attached to the upper housing, an inner wall of the cosmetic cover pushes the ends of the protrusions against an elastic force of the elastic members to set the distance between the radiating element and the inner wall of the cosmetic cover to a predetermined distance.Type: ApplicationFiled: March 28, 2008Publication date: October 2, 2008Applicant: Lenovo (Singapore) Pte. Ltd.Inventors: Hiroaki Agata, Mitsuo Horiuchi, Hirohide Komiyama, Shigeki Mori, Tetsuya Ohtani, Osamu Yamamoto
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Patent number: 7254727Abstract: An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the power consumption from power consumption in the normal-operation mode and entering the normal-operation mode when an input/output device accesses the main memory in the power-saving mode includes an attribute setting module for setting a device area of the main memory, accessed by the input/output device of the information processor to a non-cacheable attribute for exempting said device area from said coherence control even in the normal-operation mode; an operation mode setting module for allowing the input/output device to access the device area while keeping the operation mode of the information processor in the power-saving mode when the input/output device requests access to the device area in the power-saving mode.Type: GrantFiled: December 8, 2003Date of Patent: August 7, 2007Assignee: Lenovo Singapore Pte LtdInventors: Noritoshi Yoshiyama, Seiichi Kawano, Hirohide Komiyama, Tetsuji Nakamura
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Patent number: 6924442Abstract: A pen input apparatus includes a plurality of penpoints for drawing tracks on a recording medium such as paper, and a selector for selecting a specific penpoint from the plurality of penpoints. The input apparatus including a type recognition unit for recognizing the type of the selected penpoint (such as the color of a line which can be drawn, the thickness of the line, pen type such as ballpoint pen, sign pen or fluorescent pen), and a transmitter for transmitting the track of the penpoint as position information, and transmitting the information on the type recognized by the type recognition unit to a computer system.Type: GrantFiled: December 7, 2001Date of Patent: August 2, 2005Assignee: International Business Machines CorporationInventors: Masayoshi Nakano, Hirohide Komiyama, Takayuki Akai
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Publication number: 20050060591Abstract: An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the power consumption from power consumption in the normal-operation mode and entering the normal-operation mode when an input/output device accesses the main memory in the power-saving mode includes an attribute setting module for setting a device area of the main memory, accessed by the input/output device of the information processor to a non-cacheable attribute for exempting said device area from said coherence control even in the normal-operation mode; an operation mode setting module for allowing the input/output device to access the device area while keeping the operation mode of the information processor in the power-saving mode when the input/output device requests access to the device area in the power-saving mode.Type: ApplicationFiled: December 8, 2003Publication date: March 17, 2005Applicant: International Business Machines CorporationInventors: Noritoshi Yoshiyama, Seiichi Kawano, Hirohide Komiyama, Tetsuji Nakamura
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Patent number: 6778930Abstract: A computer system measures bus signal distortion and then adjusts certain characteristics of the signal transmitted over the bus, or adjusts other characteristics of the bus or the load on the bus so that signal distortion is reduced. Distortion characteristics that may be measured include signal voltage overshoot and undershoot, and data setup and hold times. Characteristics of the signal and the system that may be adjusted include changing the slew rate of the signal, changing the data setup and hold times, and changing the load impedance on the bus.Type: GrantFiled: March 29, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Takashi Sugawara, Hirohide Komiyama
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Patent number: 6728822Abstract: A jumper (60) is provided as a control input means for switching operation modes of a CardBus controller (42). Also, a bidirectional bypass path (40A, 66, 58A) is provided in parallel with the controller. When a passthrough mode signal (64) from the jumper exhibits an inactive state, the controller is enabled for operation and the bypass path is disabled for operation, thereby to cause the controller to be operated in its normal mode. On the other hand, when the passthrough mode signal exhibits an active state, the controller is disabled for operation and the bypass path is enabled for operation, thereby to cause predetermined signals on PCI bus signal lines (40A), or signals on CardBus signal lines (58A) corresponding with the predetermined signals to be output on the CardBus or PCI bus as they are via the bypass path. In order to inspect transactions on the PCI bus, a PCI bus analyzer or exerciser is connected to a PC card slot (44A), to which the bypass path is connected.Type: GrantFiled: March 10, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Takashi Sugawara, Hirohide Komiyama, Hidenobu Hanami
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Patent number: 6663430Abstract: A connector for achieving stabilization of operation of electronic equipment against EMI/ESD by reinforcing grounding of an entire connector is provided for. An interface connector has protruding portions formed on a top face and bottom face of a metal shell, wherein the height of these protruding portions is in a predetermined relationship to one another, such that the connector and connector connection structure provide: a reduction in the contact resistance in fitting portions of connectors, and hence an improvement in conductivity.Type: GrantFiled: April 11, 2001Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Hideyuki Usui, Hirohide Komiyama, Masayoshi Nakano
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Publication number: 20030140264Abstract: The present invention lowers the performance, and therefore power consumption, of a Central Processing Unit (CPU) to reduce the power consumption when the CPU encounters waiting time due to certain device-related conditions or in the course of execution of a program, thereby reducing power consumption and heat generation in an entire system. Instruction codes to be executed by a CPU and information about a performance for executing the instruction codes are loaded in the CPU and the performance of the CPU is dynamically set at a value determined based on the information about the loaded information about the performance. Thus, the CPU executes the instruction codes at the set performance.Type: ApplicationFiled: December 24, 2002Publication date: July 24, 2003Applicant: International Business Machines CorporationInventors: Seiichi Kawano, Hirohide Komiyama, Shinji Matsushima, Noritoshi Yoshiyama
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Publication number: 20020173925Abstract: A computer system measures bus signal distortion and then adjusts certain characteristics of the signal transmitted over the bus, or adjusts other characteristics of the bus or the load on the bus so that signal distortion is reduced. Distortion characteristics that may be measured include signal voltage overshoot and undershoot, and data setup and hold times. Characteristics of the signal and the system that may be adjusted include changing the slew rate of the signal, changing the data setup and hold times, and changing the load impedance on the bus.Type: ApplicationFiled: March 29, 2002Publication date: November 21, 2002Applicant: International Business Machines CorporationInventors: Takashi Sugawara, Hirohide Komiyama
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Publication number: 20020074171Abstract: A pen input apparatus includes a plurality of penpoints for drawing tracks on a recording medium such as paper, and a selector for selecting a specific penpoint from the plurality of penpoints. The input apparatus including a type recognition unit for recognizing the type of the selected penpoint (such as the color of a line which can be drawn, the thickness of the line, pen type such as ballpoint pen, sign pen or fluorescent pen), and a transmitter for transmitting the track of the penpoint as position information, and transmitting the information on the type recognized by the type recognition unit to a computer system.Type: ApplicationFiled: December 7, 2001Publication date: June 20, 2002Applicant: IBMInventors: Masayoshi Nakano, Hirohide Komiyama, Takayuki Akai
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Patent number: 6339831Abstract: A system and method for detecting connection of an external device, and for identifying the connected external device. The external device comprises: a first identification pin group consisting of one or more connector pins arranged in the longitudinal direction at one end of the connector; a second identification pin group consisting of more than one connector pins arranged in the longitudinal direction at the other end of the connector; and a control pin assigned for one pin on one end of the connector. In the external device, identification information is formed in accordance with a connection of the control pin and at least one pin among the second identification pin group, and a connection or disconnection of the control pin relative to each pin in the pin groups.Type: GrantFiled: September 11, 1998Date of Patent: January 15, 2002Assignee: International Business Machines Corp.Inventors: Takashi Sugawara, Hirohide Komiyama
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Publication number: 20010031578Abstract: A connector for achieving stabilization of operation of electronic equipment against EMI/ESD by reinforcing grounding of an entire connector is provided for. An interface connector has protruding portions formed on a top face and bottom face of a metal shell, wherein the height of these protruding portions is in a predetermined relationship to one another, such that the connector and connector connection structure provide: a reduction in the contact resistance in fitting portions of connectors, and hence an improvement in conductivity.Type: ApplicationFiled: April 11, 2001Publication date: October 18, 2001Applicant: International Business Machines CorporationInventors: Hideyuki Usui, Hirohide Komiyama, Masayoshi Nakano
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Patent number: 5404471Abstract: A data processing system has a microprocessor that is operable in real and protected address generation modes. Transition from the real mode to the protected mode is done by initializing system tables and pointer registers, switching from the real mode to the protected mode, and flushing a prefetch queue before executing further instructions in the protected mode. The transition also includes flushing instructions from the prefetch queue, immediately after the initializing, and executing at least one instruction while prefetching additional instructions that are executed to complete the transition.Type: GrantFiled: February 8, 1993Date of Patent: April 4, 1995Assignee: International Business Machines Corp.Inventors: Seiichi Kawano, Hirohide Komiyama, Shuichi Mukohyama