Patents by Inventor Hirohide MIMURA

Hirohide MIMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230090537
    Abstract: A TFT layer is provided that includes a stack of, in sequence, display wires, a protective film, a first flattening film, a metal wire layer and a second flattening film; further, a frame region has a first trench and a second trench respectively provided in the first flattening film and the second flattening film and overlapping the display wires; further, a second electrode is provided to cover the first trench and the second trench; further the protective film includes a first protective film and a third protective film formed of a silicon oxide film, and a second protective film formed of a silicon nitride film.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 23, 2023
    Inventors: Hirohide MIMURA, SHOGO MURASHIGE, YUJIRO TAKEDA
  • Publication number: 20220199657
    Abstract: A display device includes: a first gate insulating film; a first interlayer insulating film; a lower metal layer; an oxide semiconductor layer; a second gate insulating film; a second gate electrode; a second interlayer insulating film; and an upper metal layer being sequentially provided on a substrate, wherein the oxide semiconductor layer includes a second channel region and a second conductor region, the second gate insulating film is disposed in alignment with the second gate electrode, a first contact hole is provided in the first gate insulating film and the first interlayer insulating film, the lower metal layer includes a second conductor connection wiring line, a protection layer having an island shape is provided between the second conductor region and the second interlayer insulating film, a second contact hole exposing the second conductor connection wiring line is provided in the protection layer and the second interlayer insulating film.
    Type: Application
    Filed: April 17, 2019
    Publication date: June 23, 2022
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: KAZUATSU ITO, Hirohide MIMURA, MASAHITO SANO
  • Patent number: 10879064
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
  • Publication number: 20200194254
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 18, 2020
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Hirohide MIMURA, Yuhichi SAITOH, Yujiro TAKEDA, Shogo MURASHIGE, Izumi ISHIDA, Tohru OKABE