Patents by Inventor Hirohide Yano
Hirohide Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220397387Abstract: An operation accuracy measuring method for measuring the operation accuracy of a linear motion mechanism includes the steps of placing on a support table a measuring jig having a flat lower surface, a parallel surface opposite and parallel to the lower surface, and a slanted surface joined to the parallel surface through a straight boundary line, adjusting the position of the measuring jig to allow the white light interferometer to observe the parallel surface and the slanted surface simultaneously, capturing images of the parallel surface and the slanted surface with the white light interferometer and observing changes in interference fringes appearing in image sections of the captured images that represent the parallel surface and the slanted surface while the support table is being linearly moved, and the step of deducing the operation accuracy of the linear motion mechanism on the basis of the observed changes in the interference fringes.Type: ApplicationFiled: June 2, 2022Publication date: December 15, 2022Inventors: Atsushi ODA, Yoshinobu SAITO, Hirohide YANO
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Patent number: 11474143Abstract: A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.Type: GrantFiled: December 9, 2019Date of Patent: October 18, 2022Assignee: DISCO CORPORATIONInventors: Makoto Kobayashi, Okito Umehara, Yoshinobu Saito, Yusaku Ito, Hirohide Yano, Kazunari Tamura
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Publication number: 20200182923Abstract: A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.Type: ApplicationFiled: December 9, 2019Publication date: June 11, 2020Inventors: Makoto KOBAYASHI, Okito UMEHARA, Yoshinobu SAITO, Yusaku ITO, Hirohide YANO, Kazunari TAMURA
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Patent number: 9953407Abstract: A wafer inspection method includes a step of picking up an image of a processed face of a wafer, a step of extracting a pixel having a pixel value higher than those of peripheral pixels as a characteristic point from among pixels in each predetermined region of picked up image data to create a first image, and a step of extracting a pixel having a pixel value lower than those of peripheral pixels as a characteristic point from among the pixels in each predetermined region of the picked up image data to create a second image. The first and second images are used to inspect the processed face of the wafer.Type: GrantFiled: September 30, 2015Date of Patent: April 24, 2018Assignee: Disco CorporationInventors: Yusaku Ito, Hirohide Yano, Tomoyuki Yaguchi
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Patent number: 9881828Abstract: Disclosed herein is a wafer processing method including the steps of attaching a dicing tape to the back side of a wafer, the dicing tape being composed of a base tape, a DAF, and an adhesive layer for uniting the base tape and the DAF, imaging the wafer through the dicing tape to obtain an image of the wafer, detecting the positions of poor adhesion of the DAF from the image, storing the positions of poor adhesion detected above, dividing the wafer and the DAF into individual chips each having the DAF, curing the adhesive layer of the dicing tape by the application of ultraviolet light, selectively separating the chips with the DAF well adhered, at the boundary between the adhesive layer and the DAF according to the positions of poor adhesion stored above, and then picking up the chips with the DAF well adhered.Type: GrantFiled: January 20, 2017Date of Patent: January 30, 2018Assignee: DISCO CORPORATIONInventors: Shinji Yoshida, Yusaku Ito, Hirohide Yano
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Publication number: 20170213756Abstract: Disclosed herein is a wafer processing method including the steps of attaching a dicing tape to the back side of a wafer, the dicing tape being composed of a base tape, a DAF, and an adhesive layer for uniting the base tape and the DAF, imaging the wafer through the dicing tape to obtain an image of the wafer, detecting the positions of poor adhesion of the DAF from the image, storing the positions of poor adhesion detected above, dividing the wafer and the DAF into individual chips each having the DAF, curing the adhesive layer of the dicing tape by the application of ultraviolet light, selectively separating the chips with the DAF well adhered, at the boundary between the adhesive layer and the DAF according to the positions of poor adhesion stored above, and then picking up the chips with the DAF well adhered.Type: ApplicationFiled: January 20, 2017Publication date: July 27, 2017Inventors: Shinji Yoshida, Yusaku Ito, Hirohide Yano
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Patent number: 9616544Abstract: Disclosed herein is a wafer inspection method of inspecting a wafer after polishing. The wafer inspection method includes the steps of polishing the wafer after grinding, imaging a polished surface of the wafer to thereby create image data including the characteristics of plural saw marks left on the polished surface of the wafer from a detected image, performing Fourier transform to the image data to thereby extract a frequency distribution corresponding to the saw marks, performing inverse Fourier transform to the frequency distribution extracted above to obtain an amplitude of each saw mark, and determining imperfect polishing of the wafer in the case that the amplitude is greater than a predetermined range.Type: GrantFiled: August 27, 2015Date of Patent: April 11, 2017Assignee: Disco CorporationInventors: Yusaku Ito, Hirohide Yano
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Publication number: 20160098828Abstract: A wafer inspection method includes a step of picking up an image of a processed face of a wafer, a step of extracting a pixel having a pixel value higher than those of peripheral pixels as a characteristic point from among pixels in each predetermined region of picked up image data to create a first image, and a step of extracting a pixel having a pixel value lower than those of peripheral pixels as a characteristic point from among the pixels in each predetermined region of the picked up image data to create a second image. The first and second images are used to inspect the processed face of the wafer.Type: ApplicationFiled: September 30, 2015Publication date: April 7, 2016Inventors: Yusaku Ito, Hirohide Yano, Tomoyuki Yaguchi
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Publication number: 20160059375Abstract: Disclosed herein is a wafer inspection method of inspecting a wafer after polishing. The wafer inspection method includes the steps of polishing the wafer after grinding, imaging a polished surface of the wafer to thereby create image data including the characteristics of plural saw marks left on the polished surface of the wafer from a detected image, performing Fourier transform to the image data to thereby extract a frequency distribution corresponding to the saw marks, performing inverse Fourier transform to the frequency distribution extracted above to obtain an amplitude of each saw mark, and determining imperfect polishing of the wafer in the case that the amplitude is greater than a predetermined range.Type: ApplicationFiled: August 27, 2015Publication date: March 3, 2016Inventors: Yusaku Ito, Hirohide Yano