Patents by Inventor Hirohiko Inagaki
Hirohiko Inagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7555045Abstract: A picture decoding section starts to decode a bit-stream for one picture when a decoding start command is supplied from a decoding start command generating section, and outputs a decoding completion command when the decoding is completed. Decoded picture data is stored in a decoding frame buffer. The decoding frame buffer outputs a bufferfull notification when a certain quantity of picture data is stored. The decoding start command generating section outputs the decoding start command to the picture decoding section when a decoding completion command is outputted from the picture decoding section and the bufferfull notification is not outputted from the decoding frame buffer.Type: GrantFiled: July 8, 2003Date of Patent: June 30, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tadayoshi Kono, Mitsuhiko Ota, Hirohiko Inagaki
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Publication number: 20040008788Abstract: A picture decoding section starts to decode a bit-stream for one picture when a decoding start command is supplied from a decoding start command generating section, and outputs a decoding completion command when the decoding is completed. Decoded picture data is stored in a decoding frame buffer. The decoding frame buffer outputs a bufferfull notification when a certain quantity of picture data is stored. The decoding start command generating section outputs the decoding start command to the picture decoding section when a decoding completion command is outputted from the picture decoding section and the bufferfull notification is not outputted from the decoding frame buffer.Type: ApplicationFiled: July 8, 2003Publication date: January 15, 2004Applicant: FUJITSU LIMITEDInventors: Tadayoshi Kono, Mitsuhiko Ota, Hirohiko Inagaki
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Patent number: 6628719Abstract: A picture decoding section starts to decode a bit-stream for one picture when a decoding start command is supplied from a decoding start command generating section, and outputs a decoding completion command when the decoding is completed. Decoded picture data is stored in a decoding frame buffer. The decoding frame buffer outputs a bufferfull notification when a certain quantity of picture data is stored. The decoding start command generating section outputs the decoding start command to the picture decoding section when a decoding completion command is outputted from the picture decoding section and the bufferfull notification is not outputted from the decoding frame buffer.Type: GrantFiled: August 11, 1999Date of Patent: September 30, 2003Assignee: Fujitsu LimitedInventors: Tadayoshi Kono, Mitsuhiko Ota, Hirohiko Inagaki
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Patent number: 6459736Abstract: A moving picture decoding apparatus includes an input part which adds at least one picture tag to a bit stream, having a plurality of pictures, which has been subjected to intraframe or interframe encoding, the picture tag or tags having a value monotonously changing on a picture-by-picture basis, independent of picture content, a buffer memory storing the bit stream and a controller controlling one or more of the plurality of pictures stored in the buffer memory by referring to the corresponding picture tag or tags.Type: GrantFiled: June 9, 1998Date of Patent: October 1, 2002Assignee: Fujitsu LimitedInventors: Mitsuhiko Ohta, Tadayoshi Kono, Masanori Ishizuka, Hirohiko Inagaki, Koichi Yamashita
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Publication number: 20020122492Abstract: A moving picture decoding apparatus includes an input part which provides a picture tag to a bit stream which has been subjected to intraframe or interface encoding, the picture tag having a value monotonously changing on a picture base. A buffer memory stores the bit stream. A controller controls a number of pictures stored in the buffer memory by referring to the picture tag.Type: ApplicationFiled: June 9, 1998Publication date: September 5, 2002Inventors: MITSUHIKO OHTA, TADAYOSHI KONO, MASANORI ISHIZUKA, HIROHIKO INAGAKI, KOICHI YAMASHITA
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Patent number: 6408100Abstract: A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.Type: GrantFiled: September 17, 1998Date of Patent: June 18, 2002Assignee: Fujitsu LimitedInventors: Katsuki Miyawaki, Hirohiko Inagaki, Tadayoshi Kono, Mitsuhiko Ohta, Koichi Yamashita
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Publication number: 20020003902Abstract: A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.Type: ApplicationFiled: September 17, 1998Publication date: January 10, 2002Applicant: FUJITSU LIMITEDInventors: KATSUKI MIYAWAKI, HIROHIKO INAGAKI, TADAYOSHI KONO, MITSUHIKO OHTA, KOICHI YAMASHITA
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Patent number: 6011869Abstract: In storing decoded image data of a picture into a memory 23, PTS1 and a valid/invalid flag F1 corresponding to the picture are stored at the top boundary address ADR1 of a storage area within the memory 23, ADR1 is temporarily held in a register circuit 211. whether a read address ADR coincides with any one of addresses ADR1 to ADR3 within the register circuit 211 is detected while sequentially reading data from the memory 23 to display a picture. When coincidence is detected, the data read from the memory 23 are retrieved as PTS and F, and control corresponding to a time difference between STC and retrieved PTS is executed if F indicates validity. When coincidence is not detected, the data read from the memory 23 are used as display decoded image data DAT4.Type: GrantFiled: February 3, 1998Date of Patent: January 4, 2000Assignee: Fujitsu LimitedInventors: Mitsuhiko Ohta, Katsuki Miyawaki, Masanori Ishizuka, Tadayoshi Kono, Hirohiko Inagaki
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Patent number: 5991503Abstract: An encoding unit encodes and compresses picture data in a bit map format corresponding to the MPEG method. A packet assembling portion assembles the picture data encoded by the encoding unit as packets in the format corresponding to the MPEG method, and stores the packets to a storing medium. At this point, the packet assembling portion writes an I picture index to a packet that contains at least a part of I picture data. When a special reproducing operation is performed, a data storing unit reads only packets that have the I picture index. A decoding unit decodes only I picture data of picture data contained in packets read from the storing medium and displays the decoded picture data.Type: GrantFiled: June 10, 1996Date of Patent: November 23, 1999Assignee: Fujitsu LimitedInventors: Hideki Miyasaka, Hideaki Watanabe, Takehira Masanori, Kiyoshi Maeda, Masao Mutou, Hirohiko Inagaki