Patents by Inventor Hirohiko Uno

Hirohiko Uno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8115231
    Abstract: A semiconductor device includes an insulating film formed over a semiconductor substrate, a Zener diode formed above the insulating film, an interlayer film formed above the Zener diode, and a gate aluminum and a source aluminum formed above the interlayer film. The Zener diode is connected between the gate aluminum and the source aluminum. The Zener diode is formed by alternately joining an N type region and a P type region concentrically. The gate electrode includes a gate pad section. A planar shape of the Zener diode is substantially similar to a planer shape of the gate pad section. The gate pad section extends for a predetermined distance from an outermost edge of the P type region of the Zener diode to outside.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hirohiko Uno, Naoki Matsuura
  • Publication number: 20100244146
    Abstract: Provided are a semiconductor device capable of reducing a difference in wiring resistance between paths from a gate pad to a gate electrode and capable of applying a gate voltage to the gate electrode more uniformly, and a method of manufacturing the semiconductor device. The semiconductor device according to an exemplary aspect of the present invention includes a gate pad supplied with a gate voltage applied to a gate electrode of each MOSFET cell disposed in an active region, a gate connection line connected to the gate pad, and a plurality of gate lead-out lines connected in parallel between the gate electrode and the gate connection line. Each of the plurality of gate lead-out lines has a resistance value that becomes smaller by every one or plural gate lead-out lines as the gate lead-out lines are located farther away from the gate pad.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 30, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hirohiko Uno
  • Publication number: 20100019274
    Abstract: A semiconductor device includes an insulating film formed over a semiconductor substrate, a Zener diode formed above the insulating film, an interlayer film formed above the Zener diode, and a gate aluminum and a source aluminum formed above the interlayer film. The Zener diode is connected between the gate aluminum and the source aluminum. The Zener diode is formed by alternately joining an N type region and a P type region concentrically. The gate electrode includes a gate pad section. A planar shape of the Zener diode is substantially similar to a planer shape of the gate pad section. The gate pad section extends for a predetermined distance from an outermost edge of the P type region of the Zener diode to outside.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 28, 2010
    Inventors: Hirohiko Uno, Naoki Matsuura
  • Patent number: 6459122
    Abstract: A semiconductor device includes a semiconductor body having grooves, unit cell regions surrounded by the grooves, and at least a field relaxation region separated by the grooves from the unit cell regions. A gate insulating film extends within the grooves and over the field relaxation regions. Gate electrodes extend over the gate insulating film, and inter-layer insulators cover the gate electrodes. A top electrode extends over the inter-layer insulators and is in contact with parts of the unit cell regions, and the top electrode has a generally flat upper surface.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: October 1, 2002
    Assignee: NEC Corporation
    Inventor: Hirohiko Uno
  • Publication number: 20020016062
    Abstract: The present invention provides a semiconductor device comprising: a semiconductor body having grooves, unit cell regions surrounded by the grooves, at least a field relaxation region separated by the grooves from the unit cell regions; gate insulating films extending within the grooves and over the field relaxation regions; gate electrodes extending over the gate insulating film; inter-layer insulators covering the gate electrodes; and a top electrode extending over the inter-layer insulators and in contact with parts of the unit cell regions, and the top electrode having a generally flat upper surface.
    Type: Application
    Filed: July 30, 2001
    Publication date: February 7, 2002
    Applicant: NEC Corporation
    Inventor: Hirohiko Uno
  • Patent number: 6060763
    Abstract: A semiconductor device has formed onto the surface of a collector region 12 of a semiconductor substrate 11 of one conductivity type with a base region 13 of a different conductivity type, an emitter region 16 of the one conductivity type formed on a surface within the base region 13, and a base electrode 18 and emitter electrode 17 which are formed by opening windows in the base and emitter regions 13, 16.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: May 9, 2000
    Assignee: NEC Corporation
    Inventors: Kazuo Yamagishi, Akihiro Shimomura, Hirohiko Uno