Abstract: A differential coding circuit including a subtracter, a quantizer for quantizing a differential signal from the subtracter, and a predicted signal generating circuit for generating a predicted signal on the basis of a quantized differential signal from the quantizer. The subtracter subtracts the quantized differential signal of the quantizer and the predicted signal from the sampled input signal. The critical path of the circuit is shortened, therefore the operation speed of the differential coding circuit increases.

Abstract: An asynchronous signal processing circuit device having an A-D converter and a D-A converter in which a single ladder voltage generating circuit is commonly or jointly used by changing over a multiplexer during both the A-D and the D-A conversion processing. The asynchronous signal processing circuit device according to the present invention further comprises an interrupt signal generating circuit which produces an inhibit signal so as to provide a predetermined inhibit period during which the interruption by the second signal processing circuit to the first signal processing circuit is inhibited, thus preventing a misoperation of the asynchronous signal processing circuit device at the time of switching over the converters.