Patents by Inventor Hirohisa Iizuka
Hirohisa Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6828627Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.Type: GrantFiled: December 23, 2003Date of Patent: December 7, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Akira Goda, Kazuhiro Shimizu, Riichiro Shirota, Norihisa Arai, Naoki Koido, Seiichi Aritome, Tohru Maruyama, Hiroaki Hazama, Hirohisa Iizuka
-
Publication number: 20040173842Abstract: A nonvolatile semiconductor memory device having a memory cell portion and peripheral circuit portion is disclosed. The nonvolatile semiconductor memory device has peripheral transistors formed in the peripheral circuit portion of a silicon substrate and cell transistors formed in the memory cell portion of the silicon substrate. The gate length of the cell transistor is shorter than the gate length of the peripheral transistor. Further, the nonvolatile semiconductor memory device has a silicon nitride film selectively formed on the memory cell portion. The silicon nitride film covers the cell transistors.Type: ApplicationFiled: March 12, 2004Publication date: September 9, 2004Inventors: Akira Goda, Riichiro Shirota, Kazuhiro Shimizu, Hiroaki Hazama, Hirohisa Iizuka, Seiichi Aritome, Wakako Moriyama
-
Publication number: 20040135200Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.Type: ApplicationFiled: December 23, 2003Publication date: July 15, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira Goda, Kazuhiro Shimizu, Riichiro Shirota, Norihisa Arai, Naoki Koido, Seiichi Aritome, Tohru Maruyama, Hiroaki Hazama, Hirohisa Iizuka
-
Patent number: 6747311Abstract: A nonvolatile semiconductor memory device includes memory cell transistors, peripheral transistors, first post-oxidation films provided on the gate electrode of all of the memory cell transistors, second post-oxidation films provided on the gate electrode of all of the peripheral transistors, first insulating films provided on the first post-oxidation films and covering a side surface of the gate electrode of all of the memory cell transistors and second insulating films provided on the second post-oxidation films and covering a side surface of the gate electrode of all of the peripheral transistors. The first and second insulating films are harder for an oxidizing agent to pass therethrough than a silicon oxide film, and the first and second insulating films are oxidized.Type: GrantFiled: May 15, 2002Date of Patent: June 8, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Akira Goda, Riichiro Shirota, Kazuhiro Shimizu, Hiroaki Hazama, Hirohisa Iizuka, Seiichi Aritome, Wakako Moriyama
-
Publication number: 20040099900Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.Type: ApplicationFiled: July 3, 2003Publication date: May 27, 2004Inventors: Tadashi Iguchi, Katsuhiro Ishida, Hiroaki Tsunoda, Hirohisa Iizuka, Hiroaki Hazama, Seiichi Mori
-
Patent number: 6703669Abstract: A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.Type: GrantFiled: November 17, 2000Date of Patent: March 9, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Akira Goda, Kazuhiro Shimizu, Riichiro Shirota, Norihisa Arai, Naoki Koido, Seiichi Aritome, Tohru Maruyama, Hiroaki Hazama, Hirohisa Iizuka
-
Publication number: 20040041231Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.Type: ApplicationFiled: September 4, 2003Publication date: March 4, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoki Koido, Riichiro Shirota, Hirohisa Iizuka
-
Patent number: 6639296Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.Type: GrantFiled: June 15, 2001Date of Patent: October 28, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Naoki Koido, Riichiro Shirota, Hirohisa Iizuka
-
Patent number: 6462373Abstract: In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.Type: GrantFiled: November 30, 2000Date of Patent: October 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Shimizu, Riichiro Shirota, Naoki Koido, Seiichi Aritome, Hiroaki Tsunoda, Tadashi Iguchi, Kazuhito Narita, Kunihiro Terasaka, Hirohisa Iizuka
-
Publication number: 20020127802Abstract: A nonvolatile semiconductor memory device having a memory cell portion and peripheral circuit portion is disclosed. The nonvolatile semiconductor memory device has peripheral transistors formed in the peripheral circuit portion of a silicon substrate and cell transistors formed in the memory cell portion of the silicon substrate. The gate length of the cell transistor is shorter than the gate length of the peripheral transistor. Further, the nonvolatile semiconductor memory device has a silicon nitride film selectively formed on the memory cell portion. The silicon nitride film covers the cell transistors.Type: ApplicationFiled: May 15, 2002Publication date: September 12, 2002Inventors: Akira Goda, Riichiro Shirota, Kazuhiro Shimizu, Hiroaki Hazama, Hirohisa Iizuka, Seiichi Aritome, Wakako Moriyama
-
Patent number: 6413809Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.Type: GrantFiled: March 8, 2001Date of Patent: July 2, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
-
Publication number: 20010031559Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.Type: ApplicationFiled: June 15, 2001Publication date: October 18, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Naoki Koido, Riichiro Shirota, Hirohisa Iizuka
-
Patent number: 6288942Abstract: High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.Type: GrantFiled: August 4, 2000Date of Patent: September 11, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hirohisa Iizuka, Shinji Satoh, Riichiro Shirota
-
Publication number: 20010019508Abstract: In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.Type: ApplicationFiled: November 30, 2000Publication date: September 6, 2001Inventors: Kazuhiro Shimizu, Riichiro Shirota, Naoki Koido, Seiichi Aritome, Hiroaki Tsunoda, Tadashi Iguchi, Kazuhito Narita, Kunihiro Terasaka, Hirohisa Iizuka
-
Publication number: 20010018253Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.Type: ApplicationFiled: March 8, 2001Publication date: August 30, 2001Inventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
-
Patent number: 6274434Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.Type: GrantFiled: November 10, 1999Date of Patent: August 14, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Naoki Koido, Riichiro Shirota, Hirohisa Iizuka
-
Patent number: 6222225Abstract: A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.Type: GrantFiled: September 27, 1999Date of Patent: April 24, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takuya Nakamura, Naoki Koido, Hirohisa Iizuka, Kazuhito Narita, Seiichi Aritome, Fumitaka Arai
-
Patent number: 6117729Abstract: High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.Type: GrantFiled: June 12, 1998Date of Patent: September 12, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hirohisa Iizuka, Shinji Satoh, Riichiro Shirota