Abstract: A health support system that facilitates estimation of a user's health condition status and improvement of the health condition status is constructed. The health support system includes a first sensing device for acquiring biometric information of a user, a first actuator device operating based on abstracted data, and a first server connected to the first sensing device and the first actuator device via a network in a daily living space in which the user lives a daily life. The first sensing device or the server generates the abstracted data based on the biometric information. The abstracted data is classified by estimating a health condition of the user. The first actuator device facilitates improving a health condition of the user.

Abstract: In a clock signal control circuit of a semiconductor device, a first clock signal is externally supplied to a first terminal of the semiconductor device in an external clock signal mode. In an external element using mode, a second clock signal is generated on said first terminal by a clocked inverter and a self-biasing resistor composed of a P-channel MOS transistor and N-channel MOS transistor, using elements externally connected between the first terminal and a second terminal of the semiconductor device. The clock signal on said second terminal in the external clock signal mode or the external element using mode is supplied to the internal circuit of the semiconductor device using a Schnmitt trigger type of logic gate. In the external clock signal mode, the clocked inverter and the self-biasing resistor are turned off such that the generation of the second clock signal is inhibited. Further, in a clock signal stop mode, the supply of the clock signal is inhibited.

Abstract: A semiconductor integrated circuit includes transfer gates to separate a plurality of functional devices and an input or output buffer circuit, and a test circuit to connect the input buffer circuit and the output buffer circuit directly, when input, output, and input and output characteristics of the input buffer circuit and the output buffer circuit are tested. Therefore, only one test pattern is used, so that the characteristics of the buffer circuits are tested easily in a short time and exactly.