Patents by Inventor Hirohisa Masuda

Hirohisa Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230329079
    Abstract: A bismuth-based lead-free glass composition containing 70 to 84% by weight of Bi2O3, 10 to 12% by weight of ZnO, and 6 to 12% by weight of B2O3.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Toshihiko MIYAZAKI, Hirohisa MASUDA, Hiroshi SHIMOMURA, Kouji NANBU
  • Patent number: 11723262
    Abstract: A substrate for flexible device. The substrate has a nickel-plated metal sheet having a nickel-plating layer formed on at least one surface of a metal sheet or a nickel-based sheet, and a glass layer of an electrically-insulating layered bismuth-based glass on a surface of the nickel-plating layer or the nickel-based sheet. An oxide layer having a roughened surface is formed on the surface of the nickel-plating layer or the surface of the nickel-based sheet, and the bismuth-based glass contains 70 to 84% by weight of Bi2O3, 10 to 12% by weight of ZnO, and 6 to 12% by weight of B2O3. Also disclosed is a method for producing the substrate for flexible device, a substrate for an organic EL device, a sheet used as a substrate for flexible device, a method for producing the sheet and a bismuth-based lead-free glass composition.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 8, 2023
    Assignee: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Toshihiko Miyazaki, Hirohisa Masuda, Hiroshi Shimomura, Kouji Nanbu
  • Patent number: 11414762
    Abstract: A substrate for a flexible device which includes a stainless steel sheet, a nickel plating layer formed on a surface of the stainless steel sheet, and a glass layer of electrical insulating bismuth-based glass formed in the form of layer on a surface of the nickel plating layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 16, 2022
    Assignee: TOYO SEIKAN GROUP HOLDINGS. LTD.
    Inventors: Kouji Nanbu, Toshihiko Miyazaki, Hirohisa Masuda, Hiroshi Shimomura
  • Publication number: 20210343956
    Abstract: A substrate for flexible device. The substrate has a nickel-plated metal sheet having a nickel-plating layer formed on at least one surface of a metal sheet or a nickel-based sheet, and a glass layer of an electrically-insulating layered bismuth-based glass on a surface of the nickel-plating layer or the nickel-based sheet. An oxide layer having a roughened surface is formed on the surface of the nickel-plating layer or the surface of the nickel-based sheet, and the bismuth-based glass contains 70 to 84% by weight of Bi2O3, 10 to 12% by weight of ZnO, and 6 to 12% by weight of B2O3. Also disclosed is a method for producing the substrate for flexible device, a substrate for an organic EL device, a sheet used as a substrate for flexible device, a method for producing the sheet and a bismuth-based lead-free glass composition.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 4, 2021
    Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Toshihiko MIYAZAKI, Hirohisa MASUDA, Hiroshi SHIMOMURA, Kouji NANBU
  • Publication number: 20210343953
    Abstract: A substrate for flexible device, including a stainless steel sheet, an oxide layer formed on a surface of the stainless steel sheet, and a glass layer of electrically-insulating bismuth-based glass formed in a form of layer on the surface of the oxide layer. Also disclosed is a sheet for flexible device, including a stainless steel sheet, and an oxide layer on a surface of the stainless steel sheet, the oxide layer having a thickness of not less than 30 nm.
    Type: Application
    Filed: August 29, 2019
    Publication date: November 4, 2021
    Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Kouji NANBU, Toshihiko MIYAZAKI, Hirohisa MASUDA, Hiroshi SHIMOMURA
  • Patent number: 11101436
    Abstract: A substrate for flexible device. The substrate has a nickel-plated metal sheet having a nickel-plating layer formed on at least one surface of a metal sheet or a nickel-based sheet, and a glass layer of an electrically-insulating layered bismuth-based glass on a surface of the nickel-plating layer or the nickel-based sheet. An oxide layer having a roughened surface is formed on the surface of the nickel-plating layer or the surface of the nickel-based sheet, and the bismuth-based glass contains 70 to 84% by weight of Bi2O3, 10 to 12% by weight of ZnO, and 6 to 12% by weight of B2O3. Also disclosed is a method for producing the substrate for flexible device, a substrate for an organic EL device, a sheet used as a substrate for flexible device, a method for producing the sheet and a bismuth-based lead-free glass composition.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 24, 2021
    Assignee: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Toshihiko Miyazaki, Hirohisa Masuda, Hiroshi Shimomura, Kouji Nanbu
  • Publication number: 20200141009
    Abstract: A substrate for a flexible device which includes a stainless steel sheet, a nickel plating layer formed on a surface of the stainless steel sheet, and a glass layer of electrical insulating bismuth-based glass formed in the form of layer on a surface of the nickel plating layer.
    Type: Application
    Filed: June 18, 2018
    Publication date: May 7, 2020
    Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Kouji NANBU, Toshihiko MIYAZAKI, Hirohisa MASUDA, Hiroshi SHIMOMURA
  • Publication number: 20190088893
    Abstract: The present invention relates to a substrate for flexible device. The substrate has a nickel-plated metal sheet having a nickel-plating layer formed on at least one surface of a metal sheet or a nickel-based sheet, and a glass layer of an electrically-insulating layered bismuth-based glass on a surface of the nickel-plating layer or the nickel-based sheet. An oxide layer having a roughened surface is formed on the surface of the nickel-plating layer or the surface of the nickel-based sheet, and the bismuth-based glass contains 70 to 84% by weight of Bi2O3, 10 to 12% by weight of ZnO, and 6 to 12% by weight of B2O3. This substrate for flexible device is excellent in moisture barrier properties and adhesion of the glass layer, and also in a surface smoothness since occurrence of seeding and cissing on the glass layer surface can be prevented or controlled effectively.
    Type: Application
    Filed: March 22, 2017
    Publication date: March 21, 2019
    Applicant: TOYO SEIKAN GROUP HOLDINGS, LTD.
    Inventors: Toshihiko MIYAZAKI, Hirohisa MASUDA, Hiroshi SHIMOMURA, Kouji NANBU
  • Patent number: 7704837
    Abstract: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: April 27, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Publication number: 20080315258
    Abstract: A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction.
    Type: Application
    Filed: August 7, 2008
    Publication date: December 25, 2008
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Patent number: 7422945
    Abstract: In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions have first and second ends thereof. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A conductive pattern is provided to extend in the first direction across the first conductive type active region and the second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: September 9, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Patent number: 7148165
    Abstract: Disclosed is a lead-free low softening point glass whose composition lies within the system SnO—P2O5 and containing over 5 to 30 mol % of MnO. The addition of MnO allows the water resistance and coefficient of thermal expansion of the glass to be improved without spoiling its feature of a low softening point. The lead-free low softening point glass can be prepared through a simplified production process.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: December 12, 2006
    Assignee: Tokan Material Technology Co., Ltd.
    Inventor: Hirohisa Masuda
  • Publication number: 20060052230
    Abstract: Disclosed is a lead-free low softening point glass whose composition lies within the system SnO—P2O5 and containing over 5 to 30 mol % of MnO. The addition of MnO allows the water resistance and coefficient of thermal expansion of the glass to be improved without spoiling its feature of a low softening point. The lead-free low softening point glass can be prepared through a simplified production process.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 9, 2006
    Applicant: Tokan Material Technology Co., Ltd.
    Inventor: Hirohisa Masuda
  • Patent number: 6989340
    Abstract: Disclosed is a lead-free low softening point glass whose composition lies within the system SnO—P2O5 and containing over 5 to 30 mol % of MnO. The addition of MnO allows the water resistance and coefficient of thermal expansion of the glass to be improved without spoiling its feature of a low softening point. The lead-free low softening point glass can be prepared through a simplified production process.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: January 24, 2006
    Assignee: Tokan Material Technology Co., Ltd.
    Inventor: Hirohisa Masuda
  • Publication number: 20050255985
    Abstract: Disclosed is a lead-free low softening point glass whose composition lies within the system, SnO—P2O5 and containing over 5 to 30 mol % of MnO. The addition of MnO allows the water resistance and coefficient of thermal expansion of the glass to be improved without spoiling its feature of a low softening point. The lead-free low softening point glass can be prepared through a simplified production process.
    Type: Application
    Filed: May 11, 2004
    Publication date: November 17, 2005
    Applicant: Tokan Material Technology Co., Ltd.
    Inventor: Hirohisa Masuda
  • Publication number: 20050155009
    Abstract: In a method for designing a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions has first and second ends thereof. The first end of the second conductive type active regions is opposing to the second end of the first conductive type active region. In the method, a poly-silicon pattern is provided to extend in the first direction across the first conductive type active region and second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.
    Type: Application
    Filed: March 8, 2005
    Publication date: July 14, 2005
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Patent number: 6905931
    Abstract: In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions has first and second ends thereof. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern is provided to extend in the first direction across the first conductive type active region and second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: June 14, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Publication number: 20020106851
    Abstract: In a method for designing a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions has first and second ends thereof. The first end of the second conductive type active regions is opposing to the second end of the first conductive type active region. In the method, a poly-silicon pattern is provided to extend in the first direction across the first conductive type active region and second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.
    Type: Application
    Filed: April 1, 2002
    Publication date: August 8, 2002
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Patent number: 6399972
    Abstract: In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions have first and second ends thereof. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A conductive pattern is provided to extend in the first direction across the first conductive type active region and the second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: June 4, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hirohisa Masuda, Hirokazu Ishikawa
  • Patent number: 6163042
    Abstract: In order to solve the above-described problem, a semiconductor integrated circuit according to the present invention comprises a semiconductor chip, a core area formed over the semiconductor chip and comprised of predetermined circuits, and a plurality of input/output unit cells placed along peripheral edge portions of the semiconductor chip so as to surround the core area and shaped in the form of bent patterns. Further, a semiconductor integrated circuit according to another invention comprises a semiconductor chip, a core area formed over the semiconductor chip and comprised of predetermined circuits, and a plurality of input/output unit cells placed aslant toward peripheral portions of the semiconductor chip so as to surround the core area.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: December 19, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takeo Mizushima, Hirohisa Masuda