Patents by Inventor Hirohisa Ohtsuki
Hirohisa Ohtsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230223410Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: ApplicationFiled: February 9, 2023Publication date: July 13, 2023Inventors: Tokuhiko TAMAKI, Hirohisa OHTSUKI, Ryohei MIYAGAWA, Motonori ISHII
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Patent number: 11605656Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: GrantFiled: September 18, 2020Date of Patent: March 14, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tokuhiko Tamaki, Hirohisa Ohtsuki, Ryohei Miyagawa, Motonori Ishii
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Publication number: 20230042404Abstract: An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order.Type: ApplicationFiled: October 19, 2022Publication date: February 9, 2023Inventor: Hirohisa OHTSUKI
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Patent number: 11508764Abstract: An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order.Type: GrantFiled: February 27, 2020Date of Patent: November 22, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Hirohisa Ohtsuki
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Publication number: 20210005650Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Inventors: Tokuhiko TAMAKI, Hirohisa Ohtsuki, Ryohei Miyagawa, Motonori Ishii
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Patent number: 10818707Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: GrantFiled: September 13, 2018Date of Patent: October 27, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tokuhiko Tamaki, Hirohisa Ohtsuki, Ryohei Miyagawa, Motonori Ishii
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Publication number: 20200203407Abstract: An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventor: Hirohisa OHTSUKI
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Patent number: 10600826Abstract: A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.Type: GrantFiled: November 7, 2017Date of Patent: March 24, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Hirohisa Ohtsuki
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Publication number: 20190013340Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: ApplicationFiled: September 13, 2018Publication date: January 10, 2019Inventors: Tokuhiko TAMAKI, Hirohisa OHTSUKI, Ryohei MIYAGAWA, Motonori ISHII
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Patent number: 10103181Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: GrantFiled: April 14, 2017Date of Patent: October 16, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Tokuhiko Tamaki, Hirohisa Ohtsuki, Ryohei Miyagawa, Motonori Ishii
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Patent number: 10021330Abstract: In a solid-state image capturing device, one or more vertical signal lines are disposed along one of columns of a pixel portion, and each of the vertical signal lines is divided into two parts between an upper region and a lower region of the pixel portion. Pixel signals output from a plurality of pixels of the one of the columns are read out to a plurality of column readout circuits through two or more parts of the vertical signal lines including the two parts of the one or more vertical signal lines disposed along the one of the columns. A division position of one vertical signal line among the vertical signal lines disposed in the pixel portion is different from a division position of another vertical signal line among the vertical signal lines in a row direction.Type: GrantFiled: July 7, 2016Date of Patent: July 10, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hiroshi Kubo, Hirohisa Ohtsuki, Kunihiko Hara
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Patent number: 9942506Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.Type: GrantFiled: September 29, 2017Date of Patent: April 10, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Mitsuyoshi Mori, Hirohisa Ohtsuki, Yoshiyuki Ohmori, Yoshihiro Sato, Ryohei Miyagawa
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Publication number: 20180069040Abstract: A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.Type: ApplicationFiled: November 7, 2017Publication date: March 8, 2018Inventor: Hirohisa OHTSUKI
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Publication number: 20180048839Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.Type: ApplicationFiled: September 29, 2017Publication date: February 15, 2018Inventors: Mitsuyoshi MORI, Hirohisa OHTSUKI, Yoshiyuki OHMORI, Yoshihiro SATO, Ryohei MIYAGAWA
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Patent number: 9825072Abstract: A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.Type: GrantFiled: November 25, 2014Date of Patent: November 21, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Hirohisa Ohtsuki
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Patent number: 9813651Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.Type: GrantFiled: December 22, 2014Date of Patent: November 7, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Mitsuyoshi Mori, Hirohisa Ohtsuki, Yoshiyuki Ohmori, Yoshihiro Sato, Ryohei Miyagawa
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Publication number: 20170221944Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: ApplicationFiled: April 14, 2017Publication date: August 3, 2017Inventors: Tokuhiko TAMAKI, Hirohisa OHTSUKI, Ryohei MIYAGAWA, Motonori ISHII
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Patent number: 9653510Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.Type: GrantFiled: November 26, 2014Date of Patent: May 16, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Tokuhiko Tamaki, Hirohisa Ohtsuki, Ryohei Miyagawa, Motonori Ishii
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Publication number: 20160316166Abstract: In a solid-state image capturing device, one or more vertical signal lines are disposed along one of columns of a pixel portion, and each of the vertical signal lines is divided into two parts between an upper region and a lower region of the pixel portion. Pixel signals output from a plurality of pixels of the one of the columns are read out to a plurality of column readout circuits through two or more parts of the vertical signal lines including the two parts of the one or more vertical signal lines disposed along the one of the columns A division position of one vertical signal line among the vertical signal lines disposed in the pixel portion is different from a division position of another vertical signal line among the vertical signal lines in a row direction.Type: ApplicationFiled: July 7, 2016Publication date: October 27, 2016Inventors: HIROSHI KUBO, HIROHISA OHTSUKI, KUNIHIKO HARA
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Patent number: 9386248Abstract: A pixel includes: a photoelectric conversion unit that photoelectrically converts incident light and has an upper electrode, a lower electrode, and a photoelectric conversion film interposed between the upper electrode and the lower electrode; an amplifying transistor that outputs a signal according to an amount of a signal charge generated in the photoelectric conversion unit; a charge transfer line that connects the lower electrode and the amplifying transistor; and an output line that outputs the signal from the amplifying transistor, wherein at least a part of the output line is disposed to overlap the lower electrode without another line interposed therebetween.Type: GrantFiled: November 25, 2014Date of Patent: July 5, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hirohisa Ohtsuki, Akira Tanaka, Ryohei Miyagawa