Abstract: The disclosure provides for a slope voltage compensation circuit with an adaptive slope compensation method, in a DC-DC switching converter operating in current control mode, at duty cycles greater than 50%. The proposed solution allows for the dynamic range of useful operation to be extended, lowering the slope voltage compensation at the beginning of the cycle, and then increasing the compensation as 50% duty cycle is achieved. This method is based on voltage control instead of time, and a second phase of a clock is not required.

Abstract: A switching converter and a method for providing an output voltage is presented. The switching converter includes an inductor coupled to a pair of power switches, a signal generator and a controller. The first power switch is used to magnetize the inductor, while the second power switch is used to de-magnetize it. The signal generator is adapted to generate a modulated signal having a pulse width variable between a minimum value and a maximum value and to drive the first and second power switches based on the modulated signal. Upon identifying that the modulated signal has the minimum pulse width value, the controller increases a reverse current flowing from the inductor through the second power switch to prevent the output voltage from increasing above a target value.

Abstract: A thermometer-coded Digital to Analog Converter (DAC) is described, whose output is changed with fast speed, and reduced output overshoot or undershoot. The thermometer-coded DAC has selection switches and an up/down counter, with DAC codes separated into higher and lower bits. The lower bits increase up to a maximum code, then decrease. The configuration of resistors in the DAC reduces output spike, especially at the DAC code changing point.

Abstract: A thermometer-coded Digital to Analog Converter (DAC) is described, whose output is changed with fast speed, and reduced output overshoot or undershoot. The thermometer-coded DAC has selection switches and an up/down counter, with DAC codes separated into higher and lower bits. The lower bits increase up to a maximum code, then decrease. The configuration of resistors in the DAC reduces output spike, especially at the DAC code changing point.

Abstract: The disclosure provides for a slope voltage compensation circuit with an adaptive slope compensation method, in a DC-DC switching converter operating in current control mode, at duty cycles greater than 50%. The proposed solution allows for the dynamic range of useful operation to be extended, lowering the slope voltage compensation at the beginning of the cycle, and then increasing the compensation as 50% duty cycle is achieved. This method is based on voltage control instead of time, and a second phase of a clock is not required.

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p?p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p?p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p?p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p?p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract: An inductor current emulation circuit for use with a switching converter in which regulating the output voltage includes comparing an output which varies with the difference between the output voltage and a reference voltage with a ‘ramp’ signal which emulates the current in the output inductor. A current sensing circuit produces an output which varies with the current in the switching element that is turned on during the ‘off’ time, an emulated current generator circuit produces the ‘ramp’ signal during both ‘off’ and ‘on’ times, a comparator circuit compares the ‘ramp’ signal with at least one threshold voltage which varies with the sensed current and toggles an output when the ‘ramp’ exceeds the thresholds, and a feedback circuit produces an output which adjusts the ‘ramp’ signal each time the comparator circuit output toggles until the ‘ramp’ signal no longer exceeds the threshold voltages.

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p?p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p?p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract: A “windowless” H-bridge buck-boost switching converter includes a regulation circuit with an error amplifier which produces a ‘comp’ signal, a comparison circuit which compares ‘comp’ with a ‘ramp’ signal, and logic circuitry which receives the comparison circuit output and a mode control signal indicating whether the converter is to operate in buck mode or boost mode and operates the primary or secondary switching elements to produce the desired output voltage in buck or boost mode, respectively. A ‘ramp’ signal generation circuit operates to shift the ‘ramp’ signal up by a voltage Vslp(p?p)+Vhys when transitioning from buck to boost mode, and to shift ‘ramp’ back down by Vslp(p?p)+Vhys when transitioning from boost to buck mode, thereby enabling the converter to operate in buck mode or boost mode only, with no need for an intermediate buck-boost region.

Abstract: The step-down converter includes: a switch; an inductor; a rectifier; a smoothing unit; and a current bypass circuit, wherein when the current flowing toward the inductor exceeds a predetermined value, the current bypass circuit forms a path through which the current flows from the input terminal to the output terminal while bypassing the inductor.

Abstract: A reference voltage is applied from a reference voltage generating circuit to the non-inverting input terminal of an amplifier for supplying a drive voltage to the gate terminal of an NMOS transistor, and the output voltage appearing at the source terminal of the NMOS transistor is divided by a resistor pair and applied to the inverting input terminal of the amplifier. The voltage obtained by adding a voltage equal to or higher than the voltage for sufficiently driving the NMOS transistor to the output voltage appearing at the source terminal of the NMOS transistor is generated by a charge pump circuit and supplied to the amplifier as a power supply voltage. With this configuration, the drive voltage for the NMOS transistor is suppressed to the required minimum voltage while the drive voltage is obtained securely. The power consumption in the amplifier can thus be suppressed.

Abstract: A switching regulator circuit including a high-side switch and a low-side switch; an inductor having a first terminal coupled to a common terminal between the high-side switch and the low-side switch, and a second terminal coupled to an output terminal of the switching regulator circuit; a low-pass filter coupled to the first terminal of the inductor, where the low-pass filter is operative for generating a ramp signal based on the voltage signal present at the first terminal of the inductor; and a hysteretic comparator coupled to the low pass filter, where the hysteretic comparator receives the ramp signal as an input signal, and generates an output signal which is operative for controlling the operation of the high-side switch and the low-side switch.

Abstract: The present invention provides a data transmission/reception circuit which stops the operation of a packet transmission/reception circuit during a data transfer-free time thereby to realize power savings. The data transmission/reception circuit includes a packet transmission/reception circuit for performing transmission/reception of data to and from an external USB host via a USB bus at one data transfer intervals per predetermined frame, a clock generator for generating a clock signal and supplying the clock signal to the packet transmission/reception circuit, and a clock gating signal generating circuit for stopping the supply of the clock signal to the packet transmission/reception circuit by the clock generator during a frame free of the transmission/reception of the data by the packet transmission/reception circuit.

Abstract: Noise removal and detection are performed for a signal VBUS in a detection portion in accordance with a low-frequency clock signal CLK generated by a CR oscillation circuit, and a detection signal VBD is received by a process control portion. A signal VBC detected by the detection portion is supplied to a quartz oscillation circuit as an operation-enable signal ENB. Thus, when a data transmission is designated by the signal VBUS, the quartz oscillation circuit supplies a high-frequency clock signal CK to a transmission function portion, enabling a data transmission. The operation-enable signal ENB is not supplied to the quartz oscillation circuit when data transmission is not performed. The power consumption of the CR oscillation circuit is small, so power consumption can be reduced.

Abstract: A step-up converter includes an inductor which receives input voltage Vi at one end, a first FET of the first conduction type which functions as a switch for determining whether or not energy is accumulated in the inductor, a second FET of the second conduction type which rectifies a current output from the other end of the inductor, an output capacitor having an end connected to the source of the second FET, a current detection circuit, and a feedback control circuit. The current detection circuit detects a current flowing through the first N-channel FET to output current detection signal Vc. The feedback control circuit controls the operations of the first N-channel FET and a P-channel FET based on current detection signal Vc.

Abstract: A current detection circuit of the present invention has a switching device 1; an auxiliary switching device 2; an offset voltage source comprising an offset resistor device 7 and a current source circuit 8; a compensation circuit, comprising a differential amplifier 4 and a compensation transistor 5, for adjusting the output current of the auxiliary switching device 2 so that the potential obtained by subtracting the voltage drop across the offset resistor device 7 from the output potential of the switching device 1 is equal to the output potential of the auxiliary switching device 2, being configured that the detection level of the current flowing in the switching device 1 is shifted by an offset amount.

Abstract: In a DC-DC converter conforming to the current mode control system, in which the valley value of an inductor current is controlled for output control, a current detection circuit 6 is configured to detect the current flowing from a low-side FET 2 to an inductor 3 using an FET 60, an NPN transistor 61, an NPN transistor 62, a PNP transistor 64, a PNP transistor 65 and a resistor 66, to detect the current flowing from the inductor 3 to the low-side FET 2 using an FET 67, a differential amplifier 68, an FET 69 and the resistor 66, and to output a current detection signal Vc.

Abstract: A current detection circuit of the present invention has a switching device 1; an auxiliary switching device 2; an offset voltage source comprising an offset resistor device 7 and a current source circuit 8; a compensation circuit, comprising a differential amplifier 4 and a compensation transistor 5, for adjusting the output current of the auxiliary switching device 2 so that the potential obtained by subtracting the voltage drop across the offset resistor device 7 from the output potential of the switching device 1 is equal to the output potential of the auxiliary switching device 2, being configured that the detection level of the current flowing in the switching device 1 is shifted by an offset amount.

Abstract: A current detection circuit of the present invention has a switching device 1; an auxiliary switching device 2; an offset voltage source comprising an offset resistor device 7 and a current source circuit 8; a compensation circuit, comprising a differential amplifier 4 and a compensation transistor 5, for adjusting the output current of the auxiliary switching device 2 so that the potential obtained by subtracting the voltage drop across the offset resistor device 7 from the output potential of the switching device 1 is equal to the output potential of the auxiliary switching device 2, being configured that the detection level of the current flowing in the switching device 1 is shifted by an offset amount.