Patents by Inventor Hirohito Kikukawa
Hirohito Kikukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120268995Abstract: A memory cell array including non-volatile memory cells is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data. A word line select circuit and a bit line select circuit select a first word line and a first bit line connected to the second block to access the non-volatile memory cell for storing data of the second block, and selects a second word line or a second bit line connected to the first block to apply a stress voltage to the non-volatile memory cell for accumulating the degradation over time of the first block, thereby automatically detecting ambient temperature and storing accumulated stress.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: Panasonic CorporationInventors: Akira SUGIMOTO, Satoshi Mishima, Masahiro Toki, Kazuyuki Kouno, Hirohito Kikukawa, Toshio Mukunoki
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Patent number: 7884642Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: GrantFiled: March 11, 2010Date of Patent: February 8, 2011Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Publication number: 20100164542Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: ApplicationFiled: March 11, 2010Publication date: July 1, 2010Applicant: Panasonic CorporationInventors: Yasuhiro AGATA, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7696779Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: GrantFiled: September 26, 2006Date of Patent: April 13, 2010Assignee: Panasonic CorporationInventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7518903Abstract: In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, while the source line is grounded. At the time of a reset operation, bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp.Type: GrantFiled: March 1, 2007Date of Patent: April 14, 2009Assignee: Panasonic CorporationInventors: Masanori Shirahama, Yasuhiro Agata, Yasue Yamamoto, Hirohito Kikukawa
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Patent number: 7397720Abstract: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.Type: GrantFiled: August 9, 2006Date of Patent: July 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichi Sumi, Hirohito Kikukawa, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Yasue Yamamoto
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Publication number: 20070206403Abstract: In a semiconductor memory device including resistance change memory devices, when a resistance change memory device is in standby mode, the two terminals of the resistance change memory device, i.e., a bit line and a source line, are set at a precharge potential Vp by a bit-line precharge circuit and a source-line precharge circuit, respectively. At the time of a set operation, the bit line is set to a set voltage Vd, which is higher than the precharge potential Vp, by a bit-line write bias generation circuit, while the source line is grounded by a source-line write bias generation circuit. At the time of a reset operation, in contrast to the set operation, the bit line is grounded, while the source line is set to the set voltage Vd. At the time of a data-read operation, the source line is grounded by a read bias generation circuit, while the potential of the bit line is kept at the precharge potential Vp, for example.Type: ApplicationFiled: March 1, 2007Publication date: September 6, 2007Inventors: Masanori Shirahama, Yasuhiro Agata, Yasue Yamamoto, Hirohito Kikukawa
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Publication number: 20070097573Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.Type: ApplicationFiled: September 26, 2006Publication date: May 3, 2007Inventors: Yasuhiro Agata, Toshiaki Kawasaki, Masanori Shirahama, Ryuji Nishihara, Shinichi Sumi, Yasue Yamamoto, Hirohito Kikukawa
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Publication number: 20070058411Abstract: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.Type: ApplicationFiled: August 9, 2006Publication date: March 15, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shinichi Sumi, Hirohito Kikukawa, Yasuhiro Agata, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Yasue Yamamoto
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Patent number: 7136312Abstract: In a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.Type: GrantFiled: August 16, 2004Date of Patent: November 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Patent number: 6999368Abstract: A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.Type: GrantFiled: May 18, 2004Date of Patent: February 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Publication number: 20050057987Abstract: According to the invention, in a semiconductor device that needs a refresh operation for storing data, data of memory cells selected in response to a row address is read to main amplifiers through bit line pairs, sense amplifiers and data line pairs in a page-mode read operation. Thereafter, while outputting the data held in the main amplifiers to the outside, connecting transistors are turned off so as to disconnect the main amplifiers from the memory cells, and thus, the memory cells can be precharged. Also, in a page-mode write operation, while writing externally supplied input data in the main amplifiers, the memory cells can be precharged.Type: ApplicationFiled: August 16, 2004Publication date: March 17, 2005Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Publication number: 20040240299Abstract: A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.Type: ApplicationFiled: May 18, 2004Publication date: December 2, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Tomonori Fujimoto, Kiyoto Ohta, Hirohito Kikukawa
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Patent number: 6137735Abstract: The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.Type: GrantFiled: October 30, 1998Date of Patent: October 24, 2000Assignees: Mosaid Technologies Incorporated, Matsushita Electric Industrial Co., Ltd.Inventors: Fangxing Wei, Hirohito Kikukawa, Cynthia Mar
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Patent number: 5841727Abstract: To restrain an increase in power consumption and a reduction in access speed, the following structure is adopted: An address is input to a row address input circuit and in correspondence with a row address output from the row address input circuit, a predecode signal is output from a row predecode circuit. An address is input to a block-select-signal generating circuit from which first and second block select signals are output for selecting either one of the first and second memory cell array blocks. First and second predecode-signal hold circuits provided in correspondence with the first and second memory cell array blocks hold predecode signals. First and second predecode signals held by the first and second predecode signal hold circuits are supplied to first and second row decode circuits, respectively, and the first and second predecode-signal hold circuits corresponding to the first and second block select signals update the contents being held.Type: GrantFiled: June 3, 1997Date of Patent: November 24, 1998Assignee: Matsushita Electronics CorporationInventors: Shunichi Iwanari, Hirohito Kikukawa
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Patent number: 5835424Abstract: In a synchronous DRAM, a redundancy judging circuit has a frequency dividing circuit and a plurality of judging circuits each having two address comparing circuits and one output circuit. When an internal CAS signal having an activating period of time according to a data burst length, is activated, the frequency dividing circuit divides the frequency of an internal continuous clock signal having the same time period of one cycle and the same phase as those of an external clock signal, and generates complementary clock signals each having a time period of one cycle twice the time period of one cycle of the internal continuous clock signal.Type: GrantFiled: April 9, 1997Date of Patent: November 10, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirohito Kikukawa, Masashi Agata, Hironori Akamatsu
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Patent number: 5818782Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.Type: GrantFiled: March 10, 1997Date of Patent: October 6, 1998Assignee: Matsushita Electric Industrial Co.Ltd.Inventors: Hisakazu Kotani, Hironori Akamatsu, Ichiro Nakao, Toshio Yamada, Akihiro Sawada, Hirohito Kikukawa, Masashi Agata, Shunichi Iwanari
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Patent number: 5719531Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.Type: GrantFiled: October 30, 1996Date of Patent: February 17, 1998Assignee: Matsushita Electric Industrial Co.Ltd.Inventors: Hisakazu Kotani, Hironori Akamatsu, Toshio Yamada, Akihiro Sawada, Hirohito Kikukawa, Masashi Agata, Shunichi Iwanari
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Patent number: 5717651Abstract: In a synchronous DRAM, a redundancy judging circuit has a frequency dividing circuit and a plurality of judging circuits each having two address comparing circuits and one output circuit. When an internal CAS signal having an activating period of time according to a data burst length, is activated, the frequency dividing circuit divides the frequency of an internal continuous clock signal having the same time period of one cycle and the same phase as those of an external clock signal, and generates complementary clock signals each having a time period of one cycle twice the time period of one cycle of the internal continuous clock signal.Type: GrantFiled: August 31, 1995Date of Patent: February 10, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirohito Kikukawa, Masashi Agata, Hironori Akamatsu
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Patent number: 5680366Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.Type: GrantFiled: December 15, 1995Date of Patent: October 21, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hisakazu Kotani, Hironori Akamatsu, Toshio Yamada, Akihiro Sawada, Hirohito Kikukawa, Masashi Agata, Shunichi Iwanari