Abstract: The plasma display device has a plasma display panel and a driving part for driving the plasma display panel in a subframe mode. The driving part has a circuit for calculating the length of one frame based on one period of a vertical synchronizing signal introduced along with an image signal from an external device, a circuit for calculating the total number of sustaining pulses contained in one frame based on a brightness information contained in the image signal, and a circuit for calculating the length of one driving period required for displaying one frame. The length of one frame and the length of one driving period thus obtained are then compared in a comparing circuit. If the one frame length is found to be shorter than the one driving length, the total number of sustaining pulses or the number of scan lines will be reduced so that the one frame length becomes shorter than the length of one driving period, thus avoiding an extraordinary display.

Abstract: A wave generation circuit is disclosed, in which a complex waveform can be generated without increasing the ROM data amount or increasing the reading rate. Waveform data relating to a waveform and the generation thereof are stored in a ROM for each cycle. An address signal for reading the waveform data sequentially is produced sequentially by an address generation circuit. The waveform data read out are sequentially reproduced into a waveform signal by a waveform data output circuit. In a wave generating circuit including the ROM and the address generation circuit, the waveform data includes the extension information instructing to extend and reproduce the waveform data for a particular cycle.

Abstract: The present invention provides a flat display including a high-speed arithmetic logic facility so that, even when a data signal for a first line follows immediately after a frame start signal, the display displays an image with stable display quality quickly. For controlling driving signals in a flat display, each sub-frame of a temporally-segmented frame comprises at least an initialization period S1' during which a display screen is initialized, an addressing period S2 during which a plurality of cells are selected and written with display data, and a sustaining discharge period S3 during which the cells which contain display data are discharged so as to emit light for a given period of time. The flat display includes an initialization start time control unit 100 that detects the input of a display start signal V.sub.SYNC for one frame, and controls an initialization start time ST of the initialization period S1' so that the ST will precede an instant of input of a frame start signal V.sub.SYNC.

Abstract: A PDP not posing the problem that previous display data appears at the time of activation, and a wave generating circuit capable of generating a complex wave without the necessity of expanding a quantity of ROM data and of increasing a reading speed have been disclosed. A plasma display panel display comprising a plasma display panel that includes a plurality of cells to be selectively discharged to glow, a reset unit for bringing the plurality of cells to a given state, an addressing unit for setting the plurality of cells to states associated with display data, and a sustaining discharge unit for enabling the plurality of cells to glow according to the set states further comprises an operation halt factor detector for detecting the fact that a factor of halting the operation of the plasma display panel has occurred, and an initialization unit that when it is detected that the operation halt factor has occurred, initializes memory information in the plasma display panel.

Abstract: In a plasma display panel, an analogue brightness value given by a variable resistor is periodically converted into a digital brightness value and stored in a memory. A digital brightness value of a current period is compared with the digital brightness value of the next preceding period stored in the memory, to produce a difference brightness value which is compared with a predetermined brightness value and, if larger than the predetermined value, the brightness value stored in the memory is updated. Alternatively, power consumption of a display device is detected and, when the power consumption is larger than a set point, a brightness value is gradually decreased and, when the power consumption is smaller than the set point, the brightness value is gradually adjusted to a brightness set value.

Abstract: A display device, for displaying a multiple-level gray scale picture through a frame having a plurality of sub-frames which are time-divided in accordance with weight value of gray scale for each sub-frame, comprises sub-frame selection circuit, being supplied with an vertical synchronization signal, for selecting the number of the sub-frames which can be displayed within the period for the single frame in accordance with the frequency of the vertical synchronization signal, and for providing a sub-frame selection signal corresponding to the number of the sub-frames; and display control circuit, operatively connected to the sub-frame selection circuit, for receiving the sub-frame selection signal and an input display data signal and for controlling said display of the multi-level gray scale picture in accordance with the selected number of the sub-frames. When the frequency of Vsync.

Abstract: When a MOS transformer switch 14 shifts from an ON state to an OFF state, a fly-back spike voltage is induced from a secondary winding 122 to a primary winding 121. As a result electric charge accumulates in a capacitor 281, via a diode 283 and a voltage, i.e. is the voltage of a battery 10 on to which the voltage between terminals of the capacitor 281 is stacked, is supplied to the DC power-supply voltage input terminal Vcc of a control circuit 16 via a LC low pass filter 34A. Energy stored in the capacitor 281 may be effectively utilized, while the fly-back spike voltage to the control circuit 16 side is cut by a LC low pass filter 34A.