Patents by Inventor Hirohito Ohhata
Hirohito Ohhata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7187072Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: GrantFiled: November 10, 2003Date of Patent: March 6, 2007Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Publication number: 20040110319Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: ApplicationFiled: November 10, 2003Publication date: June 10, 2004Applicant: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Patent number: 6746897Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: GrantFiled: October 23, 2001Date of Patent: June 8, 2004Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Publication number: 20020094606Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: ApplicationFiled: January 8, 2002Publication date: July 18, 2002Applicant: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Publication number: 20020039808Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: ApplicationFiled: October 23, 2001Publication date: April 4, 2002Applicant: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Patent number: 6365432Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: GrantFiled: January 19, 2000Date of Patent: April 2, 2002Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Patent number: 5976912Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.Type: GrantFiled: September 18, 1996Date of Patent: November 2, 1999Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Fumio Inoue, Toshio Yamazaki, Hirohito Ohhata, Shinsuke Hagiwara, Noriyuki Taguchi, Hiroshi Nomura
-
Patent number: 5504992Abstract: The object of the present invention is to provide a wiring board fabrication process which is, not only so smooth on the surface that a fine wiring pattern can be formed thereon, but also suitable for mounting electronic parts having fine pitch terminals.The present invention is a fabrication process of a wiring board which comprises a wiring conductive line embedded in the surface of an insulating substrate so that the upper face of the conductive line and the surface of the substrate are flat, and a through-hole land which is a conductive portion projected from the surface of the substrate in a through-hole portion, which is characterized in removing the conductive portion projected from the surface of the substrate in the through-hole portion so as to have a flat surface on the surface of the substrate.Type: GrantFiled: June 30, 1994Date of Patent: April 9, 1996Assignee: Hitachi Chemical Company, Ltd.Inventors: Naoki Fukutomi, Yoshiaki Tsubomatsu, Toshio Yamazaki, Masahiko Itabashi, Hirohito Ohhata