Patents by Inventor Hirohito Taneda

Hirohito Taneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a semiconductor memory device
    Patent number: 5514607
    Abstract: When the surfaces of a selection gate electrode and a floating gate electrode are thermally oxidized with the selection gate electrode disposed below the floating gate electrode, the thickness of a gate oxide film formed on the selection gate electrode can be made larger than that of a gate oxide film formed on the other portion. As a result, the coupling ratio of a memory transistor can be increased. Thus, the coupling ratio can be adequately increased by partly increasing the thickness of the insulation film between the floating gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirohito Taneda
  • Semiconductor memory device with selection gate in a groove
    Patent number: 5359218
    Abstract: When the surfaces of a selection gate electrode and a floating gate electrode are thermally oxidized with the selection gate electrode disposed below the floating gate electrode, the thickness of a gate oxide film formed on the selection gate electrode can be made larger than that of a gate oxide film formed on the other portion. As a result, the coupling ratio of a memory transistor can be increased. Thus, the coupling ratio can be adequately increased by partly increasing the thickness of the insulation film between the floating gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: October 1, 1992
    Date of Patent: October 25, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirohito Taneda
  • Method of forming a wiring layer of a semiconductor device
    Patent number: 5190894
    Abstract: In a method of manufacturing a semiconductor device, an Al wiring layer is formed on an interlevel insulator using a positive resist. The interlevel insulator has a recess portion formed on its surface corresponding to a position between two electrodes under the interlevel insulator. The Al wiring layer extends along the recess portion in the longitudinal direction and is formed to bridge the recess portion in a direction perpendicular to the logitudinal direction. The method includes the steps of arranging an Al layer on a region of the interlevel insulator including the recess portion, arranging the resist of the Al layer, exposing the resist to a light beam using a mask member having a light-shielding portion corresponding to the wiring layer, patterning the photoresist, and etching the Al layer using the patterned resist as a mask to form the wiring layer.
    Type: Grant
    Filed: April 19, 1991
    Date of Patent: March 2, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohito Taneda, Masataka Takebuchi