Patents by Inventor Hiroho WADA

Hiroho WADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250284821
    Abstract: According to one embodiment, an information processing apparatus includes a hardware processor connected to a memory. The hardware processor extracts first file path information indicating a file path of a file used by a vulnerability inspection tool in vulnerability inspection of an object to be inspected. The file path is a file path in the object to be inspected. The hardware processor registers second file path information and the first file path information in correlation with each other in second management information. The second file path information indicates a file path to a file copied from the object to be inspected by using the first file path information.
    Type: Application
    Filed: February 19, 2025
    Publication date: September 11, 2025
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya UEHARA, Jun KANAI, Yurie SHINKE, Hiroho WADA, Hayeong SHIN, Yuto MASHIMA
  • Publication number: 20250265354
    Abstract: According to an embodiment, an information processing system includes one or more hardware processors. The one or more hardware processors are configured to: identify a threat type capable of being countered by installed software being security countermeasure software installed in a target system, from among security countermeasure software with a reported vulnerability; calculate a first risk value when a countermeasure is taken by the installed software for a threat of the identified threat type; calculate a second risk value when no countermeasure is taken by the installed software for the threat of the identified threat type; and output damage potential information including risk value change information representing a change in the second risk value with respect to the first risk value.
    Type: Application
    Filed: February 12, 2025
    Publication date: August 21, 2025
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroho WADA, Tatsuya UEHARA, Jun KANAI, Yurie SHINKE, Ryuiti KOIKE, Hayeong SHIN, Yuto MASHIMA
  • Publication number: 20250150304
    Abstract: The communication processing device of the present embodiment comprises: a first communicator to receive a message of a first communication protocol from a first communication device in a first network of a first address architecture; processing circuitry configured to, when a destination address of the received message of the first communication protocol matches a first address of the first communicator, generate a message of a second communication protocol having a payload including address information indicative of an address of a second communication device in a second network and including the message of the first communication protocol, the message of the second communication protocol requesting that the message of the first communication protocol be transferred to the second communication device; and a second communicator configured to transmit the message of the second communication protocol to a gateway device which can communicate with the second communication device in the second network.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Hiroho WADA, Naoya OHNISHI, Kohta NAKAMURA, Satoru AMAKI, Hiroshi NAKATANI, Taichi TASHIRO
  • Patent number: 12072905
    Abstract: An information processing device converts a plurality of original data arranged on a preset n-dimensional map into a plurality of new data arranged on a map according to a conversion rule. In the conversion rule, when an original datum at a target position on the map has a value of out-of-criterion, a new datum at the target position is set to the value of the original datum at the target position, and when the original datum at the target position has a value of within-criterion, each of values of one or more original data excluding an original datum having a value of the out-of-criterion from original data included in a reference region is selected to perform majority voting with the values of the one or more original data selected, and the new datum at the target position is set to a value determined by the majority voting.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 27, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroho Wada, Yoshikazu Hanatani
  • Patent number: 12039065
    Abstract: An information processing apparatus according to an embodiment includes one or more hardware processor. The one or more hardware processor divides original data into a plurality of pieces of division data, each piece of the division data including a non-overlap with one another, and executes alteration processing in mutually different manners on the plurality of pieces of division data, the mutually different manners corresponding one-to-one to the plurality of pieces of division data.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 16, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroho Wada, Naoki Ogura, Yoshikazu Hanatani
  • Publication number: 20220179874
    Abstract: An information processing device converts a plurality of original data arranged on a preset n-dimensional map into a plurality of new data arranged on a map according to a conversion rule. In the conversion rule, when an original datum at a target position on the map has a value of out-of-criterion, a new datum at the target position is set to the value of the original datum at the target position, and when the original datum at the target position has a value of within-criterion, each of values of one or more original data excluding an original datum having a value of the out-of-criterion from original data included in a reference region is selected to perform majority voting with the values of the one or more original data selected, and the new datum at the target position is set to a value determined by the majority voting.
    Type: Application
    Filed: August 27, 2021
    Publication date: June 9, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroho WADA, Yoshikazu HANATANI
  • Publication number: 20210097192
    Abstract: An information processing apparatus according to an embodiment includes one or more hardware processor. The one or more hardware processor divides original data into a plurality of pieces of division data, each piece of the division data including a non-overlap with one another, and executes alteration processing in mutually different manners on the plurality of pieces of division data, the mutually different manners corresponding one-to-one to the plurality of pieces of division data.
    Type: Application
    Filed: August 28, 2020
    Publication date: April 1, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroho WADA, Naoki OGURA, Yoshikazu HANATANI
  • Patent number: 10798580
    Abstract: According to an embodiment, an information processing device includes one or more processors configured to: receive first connected information including first information and first authentication information to authenticate the first information; add, to the first connected information, guarantee information to guarantee an anteroposterior relation of reception of the first connected information; and generate second authentication information to authenticate the first information, the guarantee information, and the first authentication information, the second authentication information being generated using the first information or the first authentication information and using the guarantee information.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: October 6, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroho Wada, Tomoko Yonemura
  • Publication number: 20180316667
    Abstract: According to an embodiment, an information processing device includes one or more processors configured to: receive first connected information including first information and first authentication information to authenticate the first information; add, to the first connected information, guarantee information to guarantee an anteroposterior relation of reception of the first connected information; and generate second authentication information to authenticate the first information, the guarantee information, and the first authentication information, the second authentication information being generated using the first information or the first authentication information and using the guarantee information.
    Type: Application
    Filed: February 16, 2018
    Publication date: November 1, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroho Wada, Tomoko Yonemura
  • Publication number: 20180310173
    Abstract: According to an embodiment, an information processing apparatus includes one or more processors. The one or more processors are configured to store, in a storage, communication data of nodes connected via a network and authentication information that is used for authentication between the nodes in communication of the communication data so that the communication data and the authentication information are associated with each other.
    Type: Application
    Filed: February 12, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoko YONEMURA, Hiroho WADA