Abstract: A radio-frequency receiver includes an RF amplification circuit which amplifies a received RF signal and generates an amplified RF signal, a mixing circuit which converts the amplified RF signal into an intermediate-frequency signal, an IF amplification circuit which generates an amplified IF signal, a first level detection circuit which detects a level of the amplified RF signal, a second level detection circuit which detects a level of the IF signal, a third level detection circuit which detects a level of the amplified IF signal, a RF reference level generation circuit which generates an RF reference level based on one of respective detection signal levels of the first and second level detection circuits, and an RF gain control circuits which controls an amplification gain of the RF amplification circuit so that a detection signal level of the third level detection circuit becomes equal to the RF reference level.

Abstract: A fast Fourier transform circuit includes a computation component, an extraction component and a setting component. The extraction component, at each step of the computation, extracts, from computation result data points calculated by the computation component, data in a pre-specified range with a number of bits the same as a predetermined number of bits, which is an effective range for a butterfly computations. The setting component sets the data points of the predetermined number of bits which have been extracted by the extraction component to serve as input data when butterfly computations of a next step are to be performed by the computation component.

Abstract: In an equalizer circuit of one aspect, a first Fourier transform circuit Fourier-transforms an input signal and outputs a corresponding first Fourier-transformed signal, and a first extracting circuit extracts a plurality of pilot symbols from the first Fourier-transformed signal. An inverse Fourier transform circuit calculates a complex gain of each path of the input signal by inverse-transforming the plurality of pilot symbols extracted by the first extracting circuit. A detecting circuit detects at least one of a power value and a mean amplitude of the input signal, and a coefficient determining circuit determines a coefficient corresponding to the at least one of the power value and the mean amplitude detected by the detecting circuit.

Abstract: A correlation calculation unit includes: four arithmetic units each including a first differential arithmetic section calculating a difference between an OFDM (orthogonal frequency division multiplexing) signal and a first delay signal, a second differential arithmetic section calculating a difference between a second delay signal and a third delay signal, and a multiplication section multiplying arithmetic results of the first and second differential arithmetic sections; four polarity conversion units converting arithmetic results of the multiplication sections of the corresponding arithmetic units into polarity signals indicating polarities of the arithmetic results, respectively; four integrating units integrating the polarity signals obtained by the corresponding polarity conversion units, respectively; and an addition unit adding up integrating results of the four integrating units, and outputting an addition result as a correlation signal indicating a correlation between the OFDM signal and the second d

Abstract: A radiofrequency signal is converted to an intermediate frequency signal by a tuner, which is amplified by a variable gain amplifier. The so-amplified signal is converted into a digital signal by an ADC, which is supplied to an FFT, where it is separated into signals set every carrier, followed by being supplied to equalizers different in characteristic. The digital signal outputted from the ADC is further supplied to a level converting circuit from which a control signal is generated. The control signal is supplied to a DAC and a Doppler frequency detector. The DAC generates a gain control signal and supplies the same to the variable gain amplifier. The Doppler frequency detector outputs a frequency component of the control signal as a Doppler detection signal. The Doppler detection signal is compared with a threshold value by a comparator. A selector selects one of signals outputted from the equalizers, in accordance with a select signal indicative of the result of comparison.

Abstract: A frequency offset detector is provided which is adaptable to a great frequency offset of one or more carrier waves in an OFDM signal. The frequency offset detector comprises a multiplication circuit which multiplies, by a pseudorandom number bit sequence, a reception signal generated by Fourier transformation of an OFDM modulated signal wherein pilot symbols are dispersed and arranged in accordance with four kinds of patterns and periodically transmitted. Four arithmetic circuits extract the pilot symbols corresponding to the respective patterns from a result of the multiplication by the multiplication circuit for each of the four kinds of patterns and calculate the sum of phase differences among the extracted pilot symbols to output an absolute value. A detection circuit detects a frequency offset on the basis of a maximum value of the absolute values calculated by the four arithmetic circuits.

Abstract: An FSK signal modulator is provided in a transmitter which receives desired information to be transmitted on its input and which modulates the information to be transmitted to transmit a binary FSK signal. A counter counts a value of addition with the value of addition modified in accordance with a predetermined rule, depending on the value specified by the information to be transmitted, and for holding the counted value . The count value is determined by a threshold value decision circuit with respect to a threshold value. The result from the decision is output in the form of binary FSK signal. An FSK signal modulator will be provided which is simplified in circuit constitution.

Abstract: A radiofrequency signal is converted to an intermediate frequency signal by a tuner, which is amplified by a variable gain amplifier. The so-amplified signal is converted into a digital signal by an ADC, which is supplied to an FFT, where it is separated into signals set every carrier, followed by being supplied to equalizers different in characteristic. The digital signal outputted from the ADC is further supplied to a level converting circuit from which a control signal is generated. The control signal is supplied to a DAC and a Doppler frequency detector. The DAC generates a gain control signal and supplies the same to the variable gain amplifier. The Doppler frequency detector outputs a frequency component of the control signal as a Doppler detection signal. The Doppler detection signal is compared with a threshold value by a comparator. A selector selects one of signals outputted from the equalizers, in accordance with a select signal indicative of the result of comparison.

Abstract: A delay profile generator that includes a delay profile generating component, a delay profile extracting component, an integrating component, a comparing component and a correcting component, is provided. The integrating component, in the delay profile extracted by the delay profile extracting component, integrates a signal component of a delay profile of a first time period, and integrates a signal component of a delay profile of a second time period that does not overlap the first time period. The comparing component compares integration values of the two time periods obtained by the integrating component. The correcting component corrects a time position of the delay profile window on the basis of results of comparison of the comparing component.

Abstract: An FSK signal modulator is provided in a transmitter which receives desired information to be transmitted on its input and which modulates the information to be transmitted to transmit a binary FSK signal. A counter counts a value of addition with the value of addition modified in accordance with a predetermined rule, depending on the value specified by the information to be transmitted, and for holding the counted value. The count value is determined by a threshold value decision circuit with respect to a threshold value. The result from the decision is output in the form of binary FSK signal. An FSK signal modulator will be provided which is simplified in circuit constitution.

Abstract: A radiofrequency signal is converted to an intermediate frequency signal by a tuner, which is amplified by a variable gain amplifier. The so-amplified signal is converted into a digital signal by an ADC, which is supplied to an FFT, where it is separated into signals set every carrier, followed by being supplied to equalizers different in characteristic. The digital signal outputted from the ADC is further supplied to a level converting circuit from which a control signal is generated. The control signal is supplied to a DAC and a Doppler frequency detector. The DAC generates a gain control signal and supplies the same to the variable gain amplifier. The Doppler frequency detector outputs a frequency component of the control signal as a Doppler detection signal. The Doppler detection signal is compared with a threshold value by a comparator. A selector selects one of signals outputted from the equalizers, in accordance with a select signal indicative of the result of comparison.

Abstract: A frequency-shift keying (FSK) signal detector includes a binarizing circuit for receiving an FSK signal and expressing amplitude of the FSK signal in binary; a correlator for receiving the FSK signal expressed in binary and acquiring a correlation of the FSK signal; and an arithmetic unit for performing an arithmetic operation on the output of the correlator to detect and output the FSK signal. The correlator includes plural stages of shift register for sequentially shifting the FSK signal in response to a clock signal; a correlation filter for obtaining the correlation by a correlation signal sequence and a window function signal sequence which obtain a correlation value at one of two frequency components generated by frequency-shift keying; and another correlation filter for obtaining the correlation by a correlation signal sequence and a window function signal sequence which obtain a correlation value at the other of the two frequency components.

Abstract: A circuit includes: a portion for performing a logical operation based on a binary modulated signal and a cyclic signal; serial-to-parallel converter for sampling a operation output for parallel output; correlation filter having multiple digital filters for allowing the parallel signal values to pass therethrough; maximum difference detector for detecting a maximum difference in a period during which a difference between the maximum and minimum output signal values from digital filters is greater than a threshold; timing detector for detecting the inversion timing of each output signal value; and decision timing exterminating portion for determining decision timing based on the maximum difference and the detected inversion timing.

Abstract: An interference wave detecting apparatus includes a first Fourier transformer for frequency-converting a received signal using Fourier transform; an extractor for extracting a known information signal from the frequency-converted received signal; an interpolator for performing interpolation to the known information signal in frequency domain, thereby generating a first transmission path estimation signal as a frequency-domain information signal; an inverse Fourier transformer for inverse-Fourier-transforming the known information signal, thereby generating a time-domain information signal; a waveform shaping section for shaping a waveform of the time-domain information signal; a second Fourier transformer for Fourier-transforming the shaped time-domain information signal, thereby generating a second transmission path estimation signal as a frequency-domain information signal; and a comparing-computing section for comparing the first and second transmission path estimation signals, thereby generating an interf

Abstract: In an FSK signal detector, an output from a limiter amplifier and an FSK signal are supplied to a comparator. The comparator has its output connected to two channels each composed of a correlator, an absolute value calculator and a digital low-pass filter in this order. The correlators calculate correlation between the output of the comparator and correlation signal strings (Cn to C2n, Dn to D2n) exhibiting certain periodicity. Outputs from the digital low-pass filters are calculated by a subtractor to be developed as demodulated data from a sign determination circuit. An FSK signal detector is provided which is capable of eliminating the adverse effect of fluctuations of an FSK signal.

Abstract: A phase-locked loop for maintaining system synchronization of a receiver with a transmitter through packet dropout. A clock signal is generated by an oscillator and the interval between the neighboring pieces of incoming system timing information is determined by a first packet counter. A second packet counter determines the interval between neighboring timing signals generated by the first packet counter. Two count values of the system timing information are retained by a delay buffer. In accordance with a value of comparison which is obtained by a difference circuit from the difference between the two count values and is larger or smaller than an error expected on system synchronization, the counter value is corrected by an overflow corrector. A cumulative offset of the clock position is corrected by a phase difference detector. The corrected offset is integrated by an integrator only at a timing of the system timing information incoming.

Abstract: There is provided an equalizer that includes: a first extracting circuit extracting a plurality of pilot symbols from an inputted signal; an inverse Fourier transform circuit inversely Fourier transforming the extracted plurality of pilot symbols, and computing a complex gain per path; a second extracting circuit extracting a plurality of paths by using the complex gains; a Fourier transform circuit Fourier transforming the extracted paths; and an equalization computing circuit extracting phase components of the Fourier-transformed paths, and carrying out multiplication by using the inputted signal and the extracted phase components.

Abstract: There is provided a channel estimating method of performing frequency conversion by a first fast Fourier transformation on a reception signal and extracting a desired signal after demodulating the reception signal, and deriving electrical energy against time delay of a channel by inverse fast Fourier transformation of the extracted result, wherein: values of a low pass filter, having an output from oversampling the input to the first fast Fourier transformation, are thinned by a plurality of thinning circuits with the same synchronization and different discrete times, and based on the outputs of the plurality of thinning circuits, the electrical energy against time delay related to the reception signal arrival time position is derived by respectively performing the first fast Fourier transformation and the inverse fast Fourier transformation.

Abstract: In an orthogonal frequency division multiplexing system using a scattered pilot signal, after equalization and Fourier transformation of the received signal, the pilot signals are extracted and further processed to generate likelihood values. In one process, the transformed signal is multiplied by the reciprocal of a variance. In another process, the transformed signal is multiplied by the reciprocal of a mean amplitude and by a weighted signal-to-interference ratio. These processes enable appropriate likelihoods to be obtained despite fast fading, shadowing, and automatic gain control.

Abstract: A radio-frequency receiver includes an RF amplification circuit which amplifies a received RF signal and generates an amplified RF signal, a mixing circuit which converts the amplified RF signal into an intermediate-frequency signal, an IF amplification circuit which generates an amplified IF signal, a first level detection circuit which detects a level of the amplified RF signal, a second level detection circuit which detects a level of the IF signal, a third level detection circuit which detects a level of the amplified IF signal, a RF reference level generation circuit which generates an RF reference level based on one of respective detection signal levels of the first and second level detection circuits, and an RF gain control circuits which controls an amplification gain of the RF amplification circuit so that a detection signal level of the third level detection circuit becomes equal to the RF reference level.