Patents by Inventor Hiroji Ebe

Hiroji Ebe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8183073
    Abstract: The method of manufacturing the semiconductor device comprises the step of forming quantum dots 16 on a base layer 10 by self-assembled growth; the step of irradiating Sb or GaSb to the surface of the base layer 10 before or in the step of forming quantum dots 16; the step of etching the surfaces of the quantum dots 16 with an As raw material gas to thereby remove an InSb layer 18 containing Sb deposited on the surfaces of the quantum dots 16; and growing a capping layer 22 on the quantum dots 16 with the InSb layer 18 removed.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: May 22, 2012
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Yasuhiko Arakawa, Denis Guimard, Shiro Tsukamoto, Hiroji Ebe, Mitsuru Sugawara
  • Publication number: 20110134950
    Abstract: The method of manufacturing the semiconductor device comprises the step of forming quantum dots 16 on a base layer 10 by self-assembled growth; the step of irradiating Sb or GaSb to the surface of the base layer 10 before or in the step of forming quantum dots 16; the step of etching the surfaces of the quantum dots 16 with an As raw material gas to thereby remove an InSb layer 18 containing Sb deposited on the surfaces of the quantum dots 16; and growing a capping layer 22 on the quantum dots 16 with the InSb layer 18 removed.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 9, 2011
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Yasuhiko Arakawa, Denis Guimard, Shiro Tsukamoto, Hiroji Ebe, Mitsuru Sugawara
  • Patent number: 7892871
    Abstract: The method of manufacturing the semiconductor device comprises the step of forming quantum dots 16 on a base layer 10 by self-assembled growth; the step of irradiating Sb or GaSb to the surface of the base layer 10 before or in the step of forming quantum dots 16; the step of etching the surfaces of the quantum dots 16 with an As raw material gas to thereby remove an InSb layer 18 containing Sb deposited on the surfaces of the quantum dots 16; and growing a capping layer 22 on the quantum dots 16 with the InSb layer 18 removed.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: February 22, 2011
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Yasuhiko Arakawa, Denis Guimard, Shiro Tsukamoto, Hiroji Ebe, Mitsuru Sugawara
  • Patent number: 7829880
    Abstract: A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number of the quantum dots and the magnitude of strain of the side barrier layer from which each of the quantum dot layers is formed are set so that a gain spectrum of the active layer has a flat gain bandwidth corresponding to a shift amount of the gain spectrum within a desired operation temperature range.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: November 9, 2010
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Hiroji Ebe, Kenichi Kawaguchi, Ken Morito, Yasuhiko Arakawa
  • Publication number: 20090305442
    Abstract: The light emitting device comprises a substrate 10 of a p-type semiconductor; an active layer 20 formed of a plurality of quantum dot layers 18 stacked, the quantum dot layers 18 having three-dimensional grown islands self-formed by S-K mode, respectively; and an n-type semiconductor layer 22 formed over the active layer. Because of the p-type semiconductor, over which the active layer 20 is formed on, and the n-type semiconductor, which is formed over the active layer 20, lower layer regions of the active layer 20, where good quantum dots 19 are formed are nearer to regions of the active layer 20, which are nearer to the p-type semiconductor. Accordingly, the radiation recombination between the holes and electrons takes place mainly in the regions where those of the quantum dots, which are of good quality. Thus, even when a number of the quantum dot layers 18 are stacked, good device characteristics can be obtained.
    Type: Application
    Filed: July 15, 2009
    Publication date: December 10, 2009
    Applicants: Fujitsu Limited, THE UNIVERSITY OF TOKYO
    Inventors: Hiroji EBE, Yoshiaki Nakata, Yasuhiko Arakawa
  • Publication number: 20080308788
    Abstract: A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number of the quantum dots and the magnitude of strain of the side barrier layer from which each of the quantum dot layers is formed are set so that a gain spectrum of the active layer has a flat gain bandwidth corresponding to a shift amount of the gain spectrum within a desired operation temperature range.
    Type: Application
    Filed: March 13, 2008
    Publication date: December 18, 2008
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Hiroji EBE, Kenichi KAWAGUCHI, Ken MORITO, Yasuhiko ARAKAWA
  • Patent number: 7456422
    Abstract: A semiconductor device including quantum dots comprises a barrier layer of a semiconductor crystal having a first lattice constant and a quantum dot layer including a plurality of quantum dots of a semiconductor crystal having a second lattice constant formed on the barrier layer and a side barrier layer of a semiconductor crystal having a third lattice constant, which is formed in contact with the side faces of the plurality of quantum dots, in which the barrier layer, the quantum dots and the side barrier layer are configured so that the difference between the values of the first lattice constant and the second lattice constant has a sign opposite to that of the difference between values of the first lattice constant and the third lattice constant.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: November 25, 2008
    Assignees: Fujitsu Limited, The University of Tokyo
    Inventors: Ayahito Uetake, Hiroji Ebe, Kenichi Kawaguchi
  • Publication number: 20080073640
    Abstract: The method of manufacturing the semiconductor device comprises the step of forming quantum dots 16 on a base layer 10 by self-assembled growth; the step of irradiating Sb or GaSb to the surface of the base layer 10 before or in the step of forming quantum dots 16; the step of etching the surfaces of the quantum dots 16 with an As raw material gas to thereby remove an InSb layer 18 containing Sb deposited on the surfaces of the quantum dots 16; and growing a capping layer 22 on the quantum dots 16 with the InSb layer 18 removed.
    Type: Application
    Filed: May 15, 2007
    Publication date: March 27, 2008
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Yasuhiko Arakawa, Denis Guimard, Shiro Tsukamoto, Hiroji Ebe, Mitsuru Sugawara
  • Publication number: 20060220001
    Abstract: A semiconductor device including quantum dots comprises a barrier layer of a semiconductor crystal having a first lattice constant and a quantum dot layer including a plurality of quantum dots of a semiconductor crystal having a second lattice constant formed on the barrier layer and a side barrier layer of a semiconductor crystal having a third lattice constant, which is formed in contact with the side faces of the plurality of quantum dots, in which the barrier layer, the quantum dots and the side barrier layer are configured so that the difference between the values of the first lattice constant and the second lattice constant has a sign opposite to that of the difference between values of the first lattice constant and the third lattice constant.
    Type: Application
    Filed: March 3, 2006
    Publication date: October 5, 2006
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Ayahito Uetake, Hiroji Ebe, Kenichi Kawaguchi
  • Publication number: 20060076552
    Abstract: The light emitting device comprises a substrate 10 of a p-type semiconductor; an active layer 20 formed of a plurality of quantum dot layers 18 stacked, the quantum dot layers 18 having three-dimensional grown islands self-formed by S-K mode, respectively; and an n-type semiconductor layer 22 formed over the active layer. Because of the p-type semiconductor, over which the active layer 20 is formed on, and the n-type semiconductor, which is formed over the active layer 20, lower layer regions of the active layer 20, where good quantum dots 19 are formed are nearer to regions of the active layer 20, which are nearer to the p-type semiconductor. Accordingly, the radiation recombination between the holes and electrons takes place mainly in the regions where those of the quantum dots, which are of good quality. Thus, even when a number of the quantum dot layers 18 are stacked, good device characteristics can be obtained.
    Type: Application
    Filed: October 12, 2005
    Publication date: April 13, 2006
    Applicants: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Hiroji Ebe, Yoshiaki Nakata, Yasuhiko Arakawa
  • Patent number: 7015498
    Abstract: A quantum semiconductor device including quantum dots formed by S-K growth process taking place in a heteroepitaxial system wherein the relationship between the energy level of light holes and the energy level of heavy holes in the valence band is changed by optimizing the in-plane strain and the vertical strain accumulated in a quantum dot.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: March 21, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Yoshiaki Nakata, Mitsuru Sugawara, Takashi Kita, Osamu Wada, Yasuhiko Arakawa
  • Patent number: 6992320
    Abstract: A semiconductor optical device having a substrate having a surface of a first semiconductor having a first lattice constant; and a semiconductor lamination layer formed on the substrate, the semiconductor lamination layer having an active layer which contains quantum dots of a first kind made of a second semiconductor having a second lattice constant in bulk state smaller than the first lattice constant. The active layer may contain quantum dots of a second kind made of a third semiconductor having a third lattice constant in bulk state larger than the first lattice constant. The quantum dots of the first and second kinds are preferably disposed alternately along the thickness direction between the barrier layers having the first lattice constant.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: January 31, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Yoshiaki Nakata, Tomoyuki Akiyama
  • Publication number: 20040124409
    Abstract: A quantum semiconductor device includes quantum dots formed by S-K growth process taking place in a heteroepitaxial system wherein the relationship between the energy level of light holes and the energy level of heavy holes in the valence band is changed by optimizing the in-plane strain and the vertical strain accumulated in a quantum dot.
    Type: Application
    Filed: September 16, 2003
    Publication date: July 1, 2004
    Inventors: Hiroji Ebe, Yoshiaki Nakata, Mitsuru Sugawara, Takashi Kita, Osamu Wada, Yasuhiko Arakawa
  • Publication number: 20040041145
    Abstract: A semiconductor optical device has: a substrate having a surface of a first semiconductor having a first lattice constant; and a semiconductor lamination layer formed on the substrate, the semiconductor lamination layer having an active layer which contains quantum dots of a first kind made of a second semiconductor having a second lattice constant in bulk state smaller than the first lattice constant. The active layer may contain quantum dots of a second kind made of a third semiconductor having a third lattice constant in bulk state larger than the first lattice constant. The quantum dots of the first and second kinds are preferably disposed alternately along the thickness direction between the barrier layers having the first lattice constant.
    Type: Application
    Filed: August 21, 2003
    Publication date: March 4, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Hiroji Ebe, Yoshiaki Nakata, Tomoyuki Akiyama
  • Patent number: 6445000
    Abstract: A first multi-quantum well structure 12 is formed on a GaAs substrate 10. The first multi-quantum well structure 12 is formed of an AlGaAs barrier layer and a GaAs well layer alternately laid one on the other to form a multi-quantum well. The GaAs barrier layer is not doped with an impurity. A second multi-quantum well structure 14 is formed on the first multi-quantum well structure 12. The second multi-quantum well structure 14 is formed of an AlGaAs barrier layer and a GaAs well layer alternately laid one on the other to form a multi-quantum well. The GaAs barrier layer is not doped with an impurity. Whereby a required electrode area can be smaller to thereby obtain higher detection sensitivity.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: September 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Prafulla Masalkar, Hiroji Ebe
  • Patent number: 5728425
    Abstract: A method and apparatus in which separate steps are used between feeding source gases and growing films in a process of chemical vapor deposition (CVD) for compound semiconductor films. In one embodiment, a CVD reactor chamber has a piston which can change the volume of the chamber to control the pressure of the source gases therein. After source gases are fed to the chamber having a substrate under the condition that no CVD takes place due to an insufficient vapor pressure, the chamber is kept closed for a few seconds, and then pressurized by the piston to start CVD. A typical result indicates that a Hg.sub.1-x Cd.sub.x Te (where x=0.2) film on a 3-inch CdTe wafer has only 1% (or .DELTA.x=0.002) inhomogeneity in composition.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: March 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Akira Sawada, Hiroshi Takigawa
  • Patent number: 5394826
    Abstract: A group II-VI epitaxial layer grown on a (111) silicon substrate has a lattice mismatch which is minimized, as between the group II-VI epitaxial layer and the silicon substrate. The grown group II-VI epitaxial layer also has a (111) plane at the interface with the substrate, and a 30.degree. in-plane rotation slip is formed at the interface between the (111) silicon substrate and the group II-VI epitaxial layer. The above structure is produced by a metal organic chemical vapor deposition method (MOCVD), in which a mol ratio of a group VI gas source supply to a group II gas source supply is kept greater than 15 during the growth. The (111) silicon substrate is preferably mis-oriented toward the <110> direction of the silicon substrate. When a HgCdTe layer is grown on the epitaxial layer, the product thus formed has utility as a monolithic infrared detector in which a plurality of detector elements are formed in the HgCdTe layer and a signal processing circuit is formed in the silicon substrate.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: March 7, 1995
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Akira Sawada
  • Patent number: 5302232
    Abstract: A group II-VI epitaxial layer grown on a (111) silicon substrate has a lattice mismatch which is minimized, as between the group II-VI epitaxial layer and the silicon substrate. The grown group II-VI epitaxial layer also has a (111) plane at the interface with the substrate, and a 30.degree. in-plane rotation slip is formed at the interface between the (111) silicon substrate and the group II-VI epitaxial layer. The above structure is produced by a metal organic chemical vapor deposition method (MOCVD), in which a mol ratio of a group VI gas source supply to a group II gas source supply is kept greater than 15 during the growth. The (111) silicon substrate is preferably mis-oriented toward the <110> direction of the silicon substrate. When a HgCdTe layer is grown on the epitaxial layer, the product thus formed has utility as a monolithic infrared detector in which a plurality of detector elements are formed in the HgCdTe layer and a signal processing circuit is formed in the silicon substrate.
    Type: Grant
    Filed: December 9, 1992
    Date of Patent: April 12, 1994
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Akira Sawada