Abstract: A logical description aiding apparatus identifies a positional relation between a position of an uncorrected description part of an after-correction logical description and a position of a corresponding description part of a before-correction logical description. After that, the logical description aiding apparatus identifies, using the identified positional relation, a position where before-correction check results are accordant with after-correction check results and conducts message replacement so that the format of a message of a before-correction check result located on the identified position is changed to the same format as the format of messages of the after-correction check results. The logical description aiding apparatus then extracts differences between the format-changed before-correction check results and the after-correction check results.

Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.

Abstract: To create a function verification description, which is used for verifying a result of simulation performed on a finite state machine, irrespective of description languages of designing an FSM and creating the function verification description even by a person without knowledge of the language and the creation method of the function verification description, there is provided an apparatus including: an extracting section for extracting data concerning a performance that is a subject for the simulation from specification data of the FSM; a retaining section for retaining one or more description templates for function verification descriptions which are associated with one or more performances that are subjects for simulation; a selecting section for selecting a description template corresponding to the first performance; and a creating section for creating the function verifying description by substituting the data concerning the first performance into the particular description template selected.

Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.

Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.

Abstract: A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.

Abstract: A circuit diagram display apparatus displays a plurality of logic circuit diagrams. An associating unit associates the logic circuits based on at least any one of identification information, structural information, logical equivalence information, and external designated information about the logic circuits. A display format changing unit changes a display format between a side-by-side format and one-below-the-other format. A display controller performs control to display a target point in the logic circuit diagram in the same position before and after the display format is changed.

Abstract: The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones.

Abstract: A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

Abstract: A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.

Abstract: A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

Abstract: An apparatus is provided for automatically modifying serious semantic grammar errors in an HDL description and to clearly show the modified portions. For these purposes, the apparatus includes: means for detecting a portion in which variables on the right and the left sides of an assignment statement are inconsistent in type; a template for converting the type of the variable on the right side of the assignment statement into that of the variable on the left side; means for modifying the portion into a correct description by applying the type conversion function to the right side of the assignment statement having the portion; and means for attaching a comment about the modification to the modified portion, and is used to automatically modify inappropriate descriptions in the design information of an electronic system or of a logic circuit described in a hardware description language such as VHDL and Verilog-HDL.

Abstract: The invention provides a circuit designing apparatus which includes a circuit information database for storing information regarding a circuit, an automatic designing processing section for reading out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database for storing design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

Abstract: The present invention relates to a timing error information managing system. This system comprises a timing error information file, a circuit information file, a correlating section for establishing a correlation between each of timing errors in the timing error information file and each of circuit configurations in the circuit information file, and for adding a circuit information pointer to the timing error information file and further for adding an error information pointer to the circuit information file, and a managing section for managing information on timing errors through the use of the circuit information pointer and the error information pointer. This configuration allows high-efficiency management of the timing error in formation, thereby achieving the speed-up of various kinds of processing using timing error information.

Abstract: The invention provides a circuit designing apparatus which includes a circuit information database for storing information regarding a circuit, an automatic designing processing section for reading out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database for storing design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.