Patents by Inventor Hiroji Yamada
Hiroji Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7450789Abstract: The present invention provides an ultra-mini and low cost refractive index measuring device applicable to biochemical measurements of an extremely minute amount of a sample. The refractive index measuring device uses a photonic crystal without any requirement of an external spectrograph or the like. The micro sensor device according to the present invention includes a light source emitting light with a single wavelength, a microcavity in which a resonant wavelength varies depending on a position thereof. A refractive index of a material to be measured is measured based on positional information by detecting a transmitting position of light changing in response to a change of a refractive index of the measured material. The micro sensor device according to the present invention enables measurement of a refractive index of a material to be measured without using a large-scale spectrograph.Type: GrantFiled: July 13, 2006Date of Patent: November 11, 2008Assignees: Hitachi, Ltd.Inventors: Kazuhiko Hosomi, Hiroji Yamada, Toshio Katsuyama, Yasuhiko Arakawa, Toshihiko Fukamachi
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Publication number: 20070073448Abstract: A semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. A hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. A wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate is used.Type: ApplicationFiled: October 20, 2006Publication date: March 29, 2007Inventors: Chisaki Takubo, Hiroji Yamada, Kazuhiro Mochizuki, Kenichi Tanaka, Tomonori Tanoue, Hiroyuki Uchiyama
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Publication number: 20070014505Abstract: The present invention provides an ultra-mini and low cost refractive index measuring device applicable to biochemical measurements of an extremely minute amount of a sample. The refractive index measuring device uses a photonic crystal without any requirement of an external spectrograph or the like. The micro sensor device according to the present invention includes a light source emitting light with a single wavelength, a microcavity in which a resonant wavelength varies depending on a position thereof. A refractive index of a material to be measured is measured based on positional information by detecting a transmitting position of light changing in response to a change of a refractive index of the measured material. The micro sensor device according to the present invention enables measurement of a refractive index of a material to be measured without using a large-scale spectrograph.Type: ApplicationFiled: July 13, 2006Publication date: January 18, 2007Inventors: Kazuhiko Hosomi, Hiroji Yamada, Toshio Katsuyama, Yasuhiko Arakawa, Toshihiko Fukamachi
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Patent number: 6984871Abstract: A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.Type: GrantFiled: May 20, 2003Date of Patent: January 10, 2006Assignee: Renesas Technology CorporationInventors: Tomonori Tanoue, Kazuhiro Mochizuki, Hiroji Yamada
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Publication number: 20050040497Abstract: The technical subject of the invention is to inhibit disconnection of electrodes caused by a step and bursting caused by residual air. That is, an object of the present invention is to provide a semiconductor device capable of overcoming a drawback due to the shape of a concave portion present in the zinc blende type compound semiconductor substrate in which the area of the bottom is larger than the surface in the cross sectional shape, as well as a manufacturing method thereof. According to the invention, a hole or step present in the semiconductor substrate constituting the semiconductor device is formed into a normal mesa shape irrespective of the orientation of the crystals on the surface of the semiconductor substrate. Accordingly, the present invention uses a novel wet etching solution having an etching rate for a portion below the etching mask higher than that in the direction of the depth of the semiconductor substrate.Type: ApplicationFiled: June 29, 2004Publication date: February 24, 2005Inventors: Chisaki Takubo, Hiroji Yamada, Kazuhiro Mochizuki, Kenichi Tanaka, Tomonori Tanoue, Hiroyuki Uchiyama
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Publication number: 20040026713Abstract: A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.Type: ApplicationFiled: May 20, 2003Publication date: February 12, 2004Applicant: Hitachi, Ltd.Inventors: Tomonori Tanoue, Kazuhiro Mochizuki, Hiroji Yamada
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Patent number: 6495914Abstract: A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of these recesses is smaller than the length of said projection, and the recesses have a higher surface smoothness than said main surfaces of said metal substrate. The metal base substrate is partially chemically etched to form the projection, and the first main surface of the substrate is mechanically worked to form at least the recesses. The conductive projection is isolated from the portion on which the bare semiconductor chip devices are mounted, of the base substrate, and the conductive projection acts as a terminal that can be electrically connected to the outside on the first and second main surfaces of the base substrate.Type: GrantFiled: February 10, 2000Date of Patent: December 17, 2002Assignee: Hitachi, Ltd.Inventors: Kenji Sekine, Hiroji Yamada, Matsuo Yamasaki, Osamu Kagaya, Kiichi Yamashita
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Patent number: 6492195Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.Type: GrantFiled: December 13, 2000Date of Patent: December 10, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Masaki Nakanishi, Susumu Sorimachi, Kiichi Yamashita, Hiroji Yamada, Kikuo Fukushima
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Publication number: 20010005043Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.Type: ApplicationFiled: December 13, 2000Publication date: June 28, 2001Inventors: Masaki Nakanishi, Susumu Sorimachi, Kiichi Yamashita, Hiroji Yamada, Kikuo Fukushima
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Patent number: 4829155Abstract: A hair styler for winding hair thereon for curling, comprising a hollow sealed tubular member made of a metallic material having good thermal conductivity and defining a heat pipe having a heat dissipating hair winding portion. The tubular member contains a charge of a working fluid vaporizable at an operating temperature of 50.degree. C. to 70.degree. C. The outer surface of the heat dissipating portion of the heat pipe is covered with an elastic hair engagement member for preventing hair slippage. The heat receiving end portion of the heat pipe is exposed so as to be adapted to receive heat from a separate external heat source having a temperature range of 50.degree. C. to 120.degree. C. Thereby hair wound around the outer surface of the heat dissipating portion of the heat pipe forming the bobbin is heated by the condensation of the vaporized working fluid within the heat pipe.Type: GrantFiled: November 21, 1986Date of Patent: May 9, 1989Assignees: Shiseido Company Ltd., The Furukawa Electric Co., Ltd.Inventors: Norifumi Fukutaka, Masatomo Kamata, Toru Watanabe, Koji Matsumoto, Tomoyuki Haga, Toshimitsu Yamagishi, Hiroji Yamada