Abstract: An information processing system which self-detects a change in the actual performance of memory elements due to mounting positions, change in environment, and aging changes to enable the memory elements to stably operate at the highest possible performance without shutting down the system. For implementing an optimal memory access for each of memory elements mounted in a memory unit, a memory controller is provided with a memory timing table which stores operation timings corresponding to the respective memory elements. The timing table is updated in response to an instruction from an apparatus for monitoring the memory operation, and the updated table is applied to a processing request after the update instruction. The apparatus for monitoring the memory operation includes an environmental sensor disposed around the memory elements, a counter for accumulating error information which is generated each time the memory unit is accessed, and so on.

Abstract: An information processing system which self-detects a change in the actual performance of memory elements due to mounting positions, change in environment, and aging changes to enable the memory elements to stably operate at the highest possible performance without shutting down the system. For implementing an optimal memory access for each of memory elements mounted in a memory unit, a memory controller is provided with a memory timing table which stores operation timings corresponding to the respective memory elements. The timing table is updated in response to an instruction from an apparatus for monitoring the memory operation, and the updated table is applied to a processing request after the update instruction. The apparatus for monitoring the memory operation includes an environmental sensor disposed around the memory elements, a counter for accumulating error information which is generated each time the memory unit is accessed, and so on.

Abstract: A fault detecting apparatus includes first and second processors having an internal state generating logic unit for exclusive-ORing the operation outputs and generating an internal state signal of the first and second processors, and a state comparator unit included in the first and second processors for comparing the internal state signals of the first and second processors. When the internal state signals fail to coincide with each other, the state comparator unit decides on an error of at least one of the first and second processors.

Abstract: A vector data processor includes a vector data buffer for receiving a plurality of arrayed data items requested from a storage including a plurality of storage banks (banks-0-3 in FIG. 2) for independent operations. The vector data buffer is constructed of a plurality of bank memories which conform to a corresponding periodic relationship between the arrayed data items and the storage banks. Date storing areas for storing the arrayed data items are preset on the successively different bank memories of the vector data buffer in the sequence in which the individual arrayed data items have been requested. The individual storage banks in the sequence in which the arrayed data items have been requested are respectively connected to the successively different bank memories, and the arrayed data items fetched from the individual storing banks are stored in the connected bank memories in succession.