Abstract: An easily dispersible cake of precipitated silica, wherein the precipitated silica has a BET specific surface area of at least 220 m2/g. When the cake is dispersed in ion-exchange water to provide an aqueous dispersion of the silica of 5% by weight in concentration and further diluted to reduce the silica concentration to 1.5% by weight, the dispersion has a light-scattering index (n-value) of at least 2. The easily dispersible cake can be obtained by simultaneously adding an alkali silicate and a mineral acid to a reaction liquid whose pH is being maintained at a fixed value within a range of 7.5-11.5 and whose temperature is being maintained at 92-98° C., thus forming precipitated silica through their reaction, and separating the precipitated silica from the reaction liquid in wet state.

Abstract: A silica cake formed of easily dispersible precipitated silica having small primary particle size is provided, from which highly transparent silica dispersion can be effectively obtained. This silica cake is characterized by being a cake of precipitated silica having BET specific surface area of at least 220 m2/g, and when it is dispersed in ion-exchange water to provide an aqueous dispersion of the silica of 5% by weight in concentration and further diluted to reduce the silica concentration to 1.5% by weight, the dispersion having a light-scattering index (n-value) of at least 2. This silica cake can be obtained by simultaneously adding an alkali silicate and a mineral acid to a reaction liquid whose pH is being maintained at a fixed value within a range of 7.5-11.5 and whose temperature is being maintained at not lower than 90° C., whereby forming precipitated silica through their reaction, and separating said precipitated silica from the reaction liquid in wet state.

Abstract: A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

Abstract: In a conventional level conversion circuit, the variation of output signals from a low level to a high level is slower than that from a high level to a low level. As a consequence, on the part of a circuit receiving signals from such a level conversion circuit, signals have to be accepted at the later signal timing, resulting in the problems of more complex timing design and of a longer time taken by signal transmission, which impedes raising the system speed.

Abstract: A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

Abstract: In a conventional level conversion circuit, the variation of output signals from a low level to a high level is slower than that from a high level to a low level. As a consequence, on the part of a circuit receiving signals from such a level conversion circuit, signals have to be accepted at the later signal timing, resulting in the problems of more complex timing design and of a longer time taken by signal transmission, which impedes raising the system speed.