Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Abstract: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

Abstract: A changing point detection circuit is provided that detects timing of changing points at which a logic value of a signal under measurement changes and includes a multi-strobe circuit generating a logic value data string obtained by detecting a logic value of the signal under measurement according to a plurality of strobes, each strobe having a different phase; a changing point detecting section detecting in which strobe the logic value changes based on the logic value data string; an edge designation storage section storing in advance information concerning whether an edge-type of the changing point to be detected is a rising edge or a falling edge of the signal under measurement; a selecting section selecting the changing point corresponding to the edge-type stored by the edge designation storage section from among the changing points detected by the changing point detecting section; and a strobe place storage section storing information concerning which strobe the changing point selected by the selecting se

Abstract: The present invention provides a test apparatus that tests a plurality of memories under test. The test apparatus includes a data input-output section that gives and receives data to and from data input-output terminals of the plurality of memories under test, a test data supplying section that parallel supplies test data to the plurality of memories under test, a writing control section that parallel supplies a write enable signal to the plurality of memories under test, a reading control section that sequentially supplies a read enable signal to each of the plurality of memories under test, a comparing section that compares the test data sequentially read from the respective memories under test with an expected value, and a detecting section that detects, on condition that one test data is not identical with the expected value, a writing fail for the memory under test that outputs this test data.

Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.

Abstract: There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.

Abstract: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.

Abstract: There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.

Abstract: A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings of defined times between edges in cycles even in a case where a capacity is large as in a test pattern for the semiconductor test equipment or a case where the cycles are away from each other.

Abstract: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal with a predetermined reference voltage and a setting voltage output section 110 for setting the voltage of the test signal to a predetermined voltage value to cause the driver 122 to terminate the transmission path of the result signal when the test apparatus reads from the device under test 15.

Abstract: The semiconductor testing apparatus includes a data sampler for acquiring a plurality of clock cross-over test data samples from the DUT using data change point detection from the sample data value and a data change point storage section writing the DCP based on CLK 1 and reading the DCP based on CLK 2 and a clock sampler acquiring a plurality of clock sample values from the DUT and a clock change point detection section detecting a clock change point from the sample value and a clock change point storage section writing the clock change point based on CLKS and reading CCP based on CLKZ using a phase difference detection section detecting the phase difference between the data change point and the clock change point which are simultaneously read from the storage section with comparison to the phase difference with the specifications data and outputting the passed or failed display indication.

Abstract: The test apparatus according to the present invention includes: a data sampler for acquiring a plurality of data sample values for data signals from the DUT; a data change point detection section for detecting a data change point from the sample value; a data change point storage section for writing the data change point based on CLK 1 and for reading the same based on CLK 2; a clock sampler for acquiring a plurality of clock sample values for clock signals from the DUT; a clock change point detection section for detecting a clock change point from the sample value; a clock change point storage section for writing the clock change point based on CLKs and reading the same based on CLK2; a phase difference detection section for detecting the phase difference between the data change point and the clock change point which are simultaneously read from the data change point storage section and the clock change point storage section; and a spec comparison section for comparing the phase difference with the spec to d

Abstract: A jitter measuring apparatus for measuring jitter of an output signal output by an electronic device is provided, wherein the jitter measuring apparatus includes a multi-strobe generating unit for generating multi-strobe having more than or equal to three (3) strobes a plurality of times synchronously with the output signal output a plurality of times by the electronic device, a value detecting unit for detecting a value of the output signal for each strobe of the multi-strobe generated a plurality of times by the multi-strobe generating unit, a transition point detecting unit for detecting the position of a transition point of the value of each output signal on the basis of the value of the output signal detected by the value detecting unit, and a histogram generating unit for counting how many times the transition point detecting unit detects the transition point at every position of the transition point of the value of the output signal.

Abstract: A jitter measuring apparatus for measuring jitter of an output signal output by an electronic device is provided, wherein the jitter measuring apparatus includes a multi-strobe generating unit for generating multi-strobe having more than or equal to three (3) strobes a plurality of times synchronously with the output signal output a plurality of times by the electronic device, a value detecting unit for detecting a value of the output signal for each strobe of the multi-strobe generated a plurality of times by the multi-strobe generating unit, a transition point detecting unit for detecting the position of a transition point of the value of each output signal on the basis of the value of the output signal detected by the value detecting unit, and a histogram generating unit for counting how many times the transition point detecting unit detects the transition point at every position of the transition point of the value of the output signal.

Abstract: A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings in cycles even in a case where a capacity is large as in a test pattern for the semiconductor test equipment or a case where compared cycles are away from each other.

Abstract: A jitter quantity calculator comprising a timing generator, a section for calculating the value of an output signal based on a timing generated by the timing generator, first and second decision sections for deciding, respectively, whether the value of an output signal from the calculating section is equal to or greater than first and second reference values, and a section for calculating the quantity of jitter of the output signal based on the decision results from the first and second decision sections, wherein the section for calculating the quantity of jitter comprises a plurality of means for calculating the quantity of jitter, and a section for selecting any one of the plurality of means and for calculating the quantity of jitter of the output signal.

Abstract: A jitter quantity calculator comprising a timing generator, a section for calculating the value of an output signal based on a timing generated by the timing generator, first and second decision sections for deciding, respectively, whether the value of an output signal from the calculating section is equal to or greater than first and second reference values, and a section for calculating the quantity of jitter of the output signal based on the decision results from the first and second decision sections, wherein the section for calculating the quantity of jitter comprises a plurality of means for calculating the quantity of jitter, and a section for selecting any one of the plurality of means and for calculating the quantity of jitter of the output signal.

Abstract: A temperature compensation circuit for an IC device delay circuit compensates fluctuations of delay time in the IC device caused by temperature changes. The temperature compensation circuit accurately compensates the temperature even when there exist deviations of electrical characteristics in the circuit components in the IC device delay circuit, such as heat dissipation by a heater. The temperature compensation circuit includes a heater to generate heat to raise temperature of the IC device delay circuit when the heater is on, a flip-flop for turning the heater off when an input signal is provided to an input terminal of the IC device delay circuit and turns the heater on when the input signal returns to the flip-flop after a selected delay time, a plurality of delay elements each having a predetermined delay time for producing delayed signals, and a selector circuit for selecting one of the delayed signals from the delay elements.

Abstract: A timing comparator circuit for use in device testing apparatus is provided which can eliminate, in the window comparison mode, an off time during which a failure cannot be detected. There are provided first and second window strobe pulse generating circuits S/RFF1 and S/RFF2 for alternately generating window strobe pulses, first and second failure detecting circuits 5a and 5b for detecting whether a failure signal exists or not in the output signals from a level comparator 2 during the pulse duration of each window strobe pulse supplied thereto from the first and the second window strobe pulse generating circuits, and first and second interleave circuits.