Patents by Inventor Hirokazu Aoki

Hirokazu Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200231062
    Abstract: An electrically driven vehicle management device is configured to acquire vehicle inherent information that can be used in identifying an electrically driven vehicle when a charging cable attachable to and detachable from the electrically driven vehicle is connected to the electrically driven vehicle, and determine, based on the acquired vehicle inherent information, a coping operation to be performed in relation to the electrically driven vehicle to which the charging cable is connected.
    Type: Application
    Filed: December 4, 2019
    Publication date: July 23, 2020
    Inventors: Atsuyuki Suzuki, Hirokazu Watanabe, Yasuaki Aoki, Masanori Takeda
  • Publication number: 20200160500
    Abstract: A prediction device includes: an acquirer configured to acquire a captured image of a scene of a section in a town and released information representing a value for the section; and a deriver configured to derive a public safety index representing a public safety state of the section in the future by inputting a result of analyzing the image and the released information to a prediction model.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 21, 2020
    Inventors: Atsuyuki Suzuki, Masanori Takeda, Yasuaki Aoki, Hirokazu Watanabe
  • Publication number: 20200160076
    Abstract: An evaluation system includes: an acquisition unit that acquires an image acquired by imaging an exterior of a vehicle; and an evaluation unit that derives and assigns an evaluation point for evaluating social credibility of a vehicle occupant of the vehicle on the basis of the image acquired by the acquisition unit.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 21, 2020
    Inventors: Atsuyuki Suzuki, Masanori Takeda, Yasuaki Aoki, Hirokazu Watanabe
  • Patent number: 6947514
    Abstract: A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: September 20, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Kazuo Kato, Takashi Sase, Takashi Hotta, Hirokazu Aoki, Kozaburo Kurita
  • Patent number: 6922113
    Abstract: The oscillation circuit includes at least two ring oscillation circuits in each of which a plurality of inverters are connected in a ring shape in a multi-stage fashion, and a conductive wiring line. The output of at least one inverter of each of the ring oscillation circuits is connected to the conductive wiring line, whereby the plurality of ring oscillators are caused to oscillate at an identical frequency. A PLL is constructed in such a way that the oscillation circuit obtained by the above means is formed into a voltage-controlled oscillation circuit, and that a phase-frequency comparator, a charge pump circuit and a low-pass filter are employed.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: July 26, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Mizuno, Hirokazu Aoki, Koichiro Ishibashi
  • Patent number: 6879188
    Abstract: A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: April 12, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Miyazaki, Ken Tatezawa, Kiwamu Takada, Kunio Uchiyama, Osamu Nishii, Kiyoshi Hasegawa, Hirokazu Aoki, Masaru Kokubo
  • Publication number: 20040100333
    Abstract: An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 27, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Mizuno, Hirokazu Aoki, Koichiro Ishibashi
  • Patent number: 6683503
    Abstract: An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase.
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: January 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Mizuno, Hirokazu Aoki, Koichiro Ishibashi
  • Publication number: 20030098730
    Abstract: A clock signal generating circuit supplies a clock signal output in a short time of 2-3 clock periods after operation starts. As a result, the clock signal generating circuit can be stopped simultaneously when the operation of an internal circuit is put in a stop state, the clock signal generating circuit can output a clock signal when the internal circuit returns to the operating state, and power consumption when the internal circuit is in the stop state is reduced.
    Type: Application
    Filed: December 19, 2002
    Publication date: May 29, 2003
    Inventors: Masayuki Miyazaki, Ken Tatezawa, Kiwamu Takada, Kunio Uchiyama, Osamu Nishii, Kiyoshi Hasegawa, Hirokazu Aoki, Masaru Kokubo
  • Patent number: 6515519
    Abstract: A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: February 4, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Miyazaki, Ken Tatezawa, Kiwamu Takada, Kunio Uchiyama, Osamu Nishii, Kiyoshi Hasegawa, Hirokazu Aoki, Masaru Kokubo
  • Patent number: 6489824
    Abstract: A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: December 3, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Miyazaki, Koichiro Ishibashi, Takeshi Sakata, Satoru Hanzawa, Hiroyuki Mizuno, Kiyoshi Hasegawa, Masaru Kokubo, Hirokazu Aoki
  • Publication number: 20020003452
    Abstract: An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase.
    Type: Application
    Filed: August 27, 1998
    Publication date: January 10, 2002
    Inventors: HIROYUKI MIZUNO, HIROKAZU AOKI, KOICHIRO ISHIBASHI
  • Publication number: 20020000851
    Abstract: A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
    Type: Application
    Filed: August 24, 2001
    Publication date: January 3, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Masayuki Miyazaki, Koichiro Ishibashi, Takeshi Sakata, Satoru Hanzawa, Hiroyuki Mizuno, Kiyoshi Hasegawa, Masaru Kokubo, Hirokazu Aoki
  • Patent number: 6300807
    Abstract: A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: October 9, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masayuki Miyazaki, Koichiro Ishibashi, Takeshi Sakata, Satoru Hanzawa, Hiroyuki Mizuno, Kiyoshi Hasegawa, Masaru Kokubo, Hirokazu Aoki
  • Patent number: 5454087
    Abstract: An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: September 26, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Hirokazu Aoki
  • Patent number: 5287484
    Abstract: A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: February 15, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Osamu Nishii, Kunio Uchiyama, Hirokazu Aoki, Takashi Kikuchi, Yasuhiko Saigou
  • Patent number: 5283886
    Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: February 1, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Nishii, Kunio Uchiyama, Hirokazu Aoki, Kanji Oishi, Jun Kitano, Susumu Hatano
  • Patent number: 5267198
    Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: November 30, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta, Kunio Uchiyama, Hirokazu Aoki, Osamu Nishii
  • Patent number: 5202969
    Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: April 13, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering
    Inventors: Katsuyuki Sato, Tadahiko Nishimukai, Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi, Hiroshi Fukuta, Takashi Kikuchi, Yasuhiko Saigou
  • Patent number: 5193075
    Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: March 9, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Susumu Hatano, Kanji Oishi, Takashi Kikuchi, Yasuhiko Saigou, Hiroshi Fukuta, Kunio Uchiyama, Hirokazu Aoki, Osamu Nishii