Patents by Inventor Hirokazu ATOU

Hirokazu ATOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE FOR REDUCING INTERCONNECT PITCH
    Publication number: 20120256243
    Abstract: A semiconductor device includes a plurality of transistors formed on a semiconductor substrate, a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction, a second local wiring which is formed above the first local wiring and which electrically connects to at least one of the plurality of transistors and extends in a second direction, a plurality of first wirings which are formed above the second local wiring and which extend in a third direction, at least each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively, and a second wiring which is formed above the first wiring and which electrically connects to at least one of the plurality of first wirings and extends in a fourth direction.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 11, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hirokazu ATOU, Hisayuki NAGAMINE