Patents by Inventor Hirokazu Fujiwara
Hirokazu Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10020390Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.Type: GrantFiled: August 4, 2014Date of Patent: July 10, 2018Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
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Patent number: 9954096Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.Type: GrantFiled: July 31, 2017Date of Patent: April 24, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu Fujiwara, Yuichi Takeuchi, Narumasa Soejima
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Publication number: 20180090612Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.Type: ApplicationFiled: July 31, 2017Publication date: March 29, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu FUJIWARA, Yuichi TAKEUCHI, Narumasa SOEJIMA
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Patent number: 9899469Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.Type: GrantFiled: December 11, 2015Date of Patent: February 20, 2018Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Shinya Nishimura, Hirokazu Fujiwara, Narumasa Soejima, Yuichi Takeuchi
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Patent number: 9853141Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.Type: GrantFiled: August 4, 2014Date of Patent: December 26, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
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Publication number: 20170317162Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.Type: ApplicationFiled: December 11, 2015Publication date: November 2, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Shinya NISHIMURA, Hirokazu FUJIWARA, Narumasa SOEJIMA, Yuichi TAKEUCHI
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Patent number: 9780205Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.Type: GrantFiled: August 4, 2014Date of Patent: October 3, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
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Patent number: 9612215Abstract: The invention provides a susceptor capable of obtaining high-quality SiC semiconductor crystals by keeping the Si concentration and C concentration around a wafer constant and by preventing the generation of particles. A susceptor of graphite covered with silicon carbide is characterized in that at least one section of a part on which a wafer is placed is tantalum carbide or a graphite material covered with tantalum carbide. The part on which the wafer is placed may be a detachable member. A material around the part on which the wafer is placed may be a detachable graphite material covered with silicon carbide.Type: GrantFiled: July 1, 2005Date of Patent: April 4, 2017Assignee: TOYO TANSO CO., LTD.Inventors: Ichiro Fujita, Hirokazu Fujiwara
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Patent number: 9607836Abstract: A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.Type: GrantFiled: September 24, 2013Date of Patent: March 28, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu Fujiwara, Narumasa Soejima
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Publication number: 20170040446Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.Type: ApplicationFiled: August 4, 2014Publication date: February 9, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
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Publication number: 20170012121Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.Type: ApplicationFiled: August 4, 2014Publication date: January 12, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
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Publication number: 20160329422Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.Type: ApplicationFiled: August 4, 2014Publication date: November 10, 2016Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
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Patent number: 9201094Abstract: A wafer examination device includes a probe, a fusion section and a measurement section. The probe is made of a metal which reacts with silicon carbide to produce silicide. The fusion section fuses the probe to a silicon carbide wafer as an examined object. The measurement section measures an electrical property of the silicon carbide wafer through the fused probe.Type: GrantFiled: December 9, 2013Date of Patent: December 1, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hirokazu Fujiwara, Narumasa Soejima
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Patent number: 9142411Abstract: A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.Type: GrantFiled: November 26, 2013Date of Patent: September 22, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masatoshi Tsujimura, Hirokazu Fujiwara, Tomoo Morino, Narumasa Soejima
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Publication number: 20150214052Abstract: A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.Type: ApplicationFiled: September 24, 2013Publication date: July 30, 2015Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu Fujiwara, Narumasa Soejima
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Publication number: 20140162443Abstract: A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.Type: ApplicationFiled: November 26, 2013Publication date: June 12, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masatoshi TSUJIMURA, Hirokazu FUJIWARA, Tomoo MORINO, Narumasa SOEJIMA
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Publication number: 20140159705Abstract: A wafer examination device includes a probe, a fusion section and a measurement section. The probe is made of a metal which reacts with silicon carbide to produce silicide. The fusion section fuses the probe to a silicon carbide wafer as an examined object. The measurement section measures an electrical property of the silicon carbide wafer through the fused probe.Type: ApplicationFiled: December 9, 2013Publication date: June 12, 2014Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu Fujiwara, Narumasa Soejima
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Patent number: 8748975Abstract: A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.Type: GrantFiled: December 12, 2012Date of Patent: June 10, 2014Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Hirokazu Fujiwara, Yukihiko Watanabe, Narumasa Soejima, Toshimasa Yamamoto, Yuichi Takeuchi
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Patent number: 8470672Abstract: A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.Type: GrantFiled: August 30, 2011Date of Patent: June 25, 2013Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki KaishaInventors: Takeshi Endo, Shinichiro Miyahara, Tomoo Morino, Masaki Konishi, Hirokazu Fujiwara, Jun Morimoto, Tsuyoshi Ishikawa, Takashi Katsuno, Yukihiko Watanabe
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Publication number: 20130146969Abstract: A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.Type: ApplicationFiled: December 12, 2012Publication date: June 13, 2013Inventors: Hirokazu FUJIWARA, Yukihiko WATANABE, Narumasa SOEJIMA, Toshimasa YAMAMOTO, Yuichi TAKEUCHI