Abstract: Provided is an organic-inorganic composite membrane for a multilayer heat-resistant separator material, having smoothness, maintenance of microporous characteristics of a substrate film, and adhesion between a substrate and a heat-resistant layer in a well-balanced manner. The organic-inorganic composite membrane is provided with the heat-resistant layer containing inorganic heat-resistant particles and an organic solvent-soluble binder on at least one surface of the substrate film formed of a microporous membrane made of polyolefin, in which the inorganic heat-resistant particles contain small particles F(a) having an average particle size less than 0.2 micrometer and large particles F(b) having an average particle size of 0.2 micrometer or more.

Abstract: The objective of the present disclosure is to show a multilayered heat-resistant separator element having minimized warpage and curling. The present disclosure is a multilayered heat-resistant separator element obtained by laminating an inorganic heat-resistant layer on at least one surface of a substrate film comprising a polyolefin microporous membrane having an elongation of 2% or less when tensioned at 10 N/mm2 at 100° C., the curl height of the multilayered heat-resistant separator element not exceeding 10 mm. During manufacturing of the multilayered heat-resistant separator element, the inorganic heat-resistant layer is dried and solidified at a temperature of 80 to 120° C. and a tensile force of 4-10 N/mm2.

Abstract: The present invention addresses the problem of providing an organic-inorganic composite film that is useful as a separator material. The problem is addressed by an organic-inorganic composite film characterized in that a heat-resistant layer that contains inorganic heat resistant particles and a binder is provided on at least one surface of a base material film comprising a polyolefin microporous film, said organic-inorganic composite film satisfying all of the following conditions (A), (B), and (C): Condition (A): a?1.5 (a: density of heat resistant layer (g/m2/?m), condition (B): 12.74?b (b: peel strength (N) of base material film and heat resistant layer), condition (C): c?20 (c: represents the percentage change in air permeability (%) calculated from the following equation. Percentage change in air permeability (%)=|(air permeability of organic-inorganic composite film)?(air permeability of base material film)|÷(air permeability of base material film)×100).

Abstract: Provided is a cultivation system comprising: a cultivation container capable of accommodating a plurality of plants and a cultivation medium for growing the plant, and provided with a recording medium for recording identification information that is used for identifying each of the plurality of plant; a cultivation shelf provided with plural stages of shelf boards on which the cultivation container is placed; light sources projecting light individually onto upper faces of the shelf boards; a conveyance machine conveying the cultivation container between the plurality of shelf boards. The cultivation system is additionally provided with: an inspection part which has an accommodation part accommodating the cultivation container, and inspects individually the plurality of plants contained in the cultivation container accommodated in the accommodation part; and a recording processing part recording an inspection result each of plant obtained by the inspection part, into the recording medium.

Abstract: Provided is a method for manufacturing a semiconductor device in which movement of an island in resin sealing is prevented. A molding die includes an upper die and a lower die. The upper and lower dies are fitted together to form cavities and runners. In the lower die, a pod is provided. After heating and melting of a tablet made of a solid resin and housed in the pod, the melted sealing resin is pressurized by a plunger, and is supplied to each of the cavities. Specifically, a liquid sealing resin is supplied from the pod to the cavities, sequentially, from the upstream of the flow of the sealing resin supplied from the pod. The cavities communicate with each other through the runners. Furthermore, the runners through which the cavities communicate are provided to be tilted with respect to a path for supplying the sealing resin.

Abstract: A semiconductor device in which overall thickness is reduced by suppressing the rising of a metal thin line and connection reliability is enhanced at the joint of metal thin line and other member during resin sealing. A method for manufacturing such semiconductor device is also provided. The semiconductor device (10A) comprises electrodes (12A, 12B, 12C), a semiconductor chip (13) bonded to the upper surface of the electrode (12A) formed in the shape of island, a metal thin line (15A) connecting the semiconductor chip (13) and the electrode (12C), a metal thin line (15B) connecting the semiconductor chip (13) and the electrode (12B), and a sealing resin (11) supporting those elements mechanically by sealing them integrally. The metal thin lines (15A, 15B) have planar shape curved convexly toward the upstream of the flow if the sealing resin (11) to be injected.

Abstract: Provided is a method for manufacturing a semiconductor device in which movement of an island in resin sealing is prevented. A molding die includes an upper die and a lower die. The upper and lower dies are fitted together to form cavities and runners. In the lower die, a pod is provided. After heating and melting of a tablet made of a solid resin and housed in the pod, the melted sealing resin is pressurized by a plunger, and is supplied to each of the cavities. Specifically, a liquid sealing resin is supplied from the pod to the cavities, sequentially, from the upstream of the flow of the sealing resin supplied from the pod. The cavities communicate with each other through the runners. Furthermore, the runners through which the cavities communicate are provided to be tilted with respect to a path for supplying the sealing resin.

Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract: A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Abstract: A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET, and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Abstract: A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

Abstract: Recently, there have been increasing demands for the reduction in size and weight of mobile computing/communication terminals as well as the elongation of the use time of the internal batteries. This invention alters the assembling structure of power MOSFET for reducing the on-state resistance and improving the production efficiency. This semiconductor device includes a lower frame having a header 2 for fixing a semiconductor chip and corresponding external leads 3d, 3g, a semiconductor chip fixed on the header, an upper frame 7 having a connection electrode 6 fixed on a current passage electrode 5 formed on the top face of the semiconductor chip 1 and the corresponding leads 3s, and a resin mold 8. This two-frame configuration provides extremely low on-state resistance and good production efficiency.

Abstract: After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.

Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

Abstract: After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.

Abstract: Recently, there have been increasing demands for the reduction in size and weight of mobile computing/communication terminals as well as the elongation of the use time of the internal batteries. This invention alters the assembling structure of power MOSFET for reducing the on-state resistance and improving the production efficiency. This semiconductor device includes a lower frame having a header 2 for fixing a semiconductor chip and corresponding external leads 3d, 3g, a semiconductor chip fixed on the header, an upper frame 7 having a connection electrode 6 fixed on a current passage electrode 5 formed on the top face of the semiconductor chip 1 and the corresponding leads 3s, and a resin mold 8. This two-frame configuration provides extremely low on-state resistance and good production efficiency.