Patents by Inventor Hirokazu Goto
Hirokazu Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240383442Abstract: An authentication device to be mounted on a vehicle includes a processor. The processor is configured to execute first authentication based on biometric information acquired from a user and biometric information preregistered in the vehicle. The processor is configured to execute second authentication different from the first authentication. The processor is configured to transit setting of the first authentication to a state in which the user is able to change the setting, when the second authentication is successful.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, Kabushiki Kaisha Tokai Rika Denki SeisakushoInventors: Yuya GOTO, Naoyuki TAKADA, Kosuke TAKI, Daisuke OGAWA, Hirokazu ITAKURA, Takahiko ANDO
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Patent number: 12077129Abstract: An authentication device to be mounted on a vehicle includes a processor. The processor is configured to execute first authentication based on biometric information acquired from a user and biometric information preregistered in the vehicle. The processor is configured to execute second authentication based on identification information acquired from a mobile device of the user and identification information preregistered in the vehicle. The processor is configured to permit start of the vehicle when at least one of the first authentication and the second authentication is successful. The processor is configured to set an authentication function of the first authentication from ON to OFF when at least one of the first authentication and the second authentication is successful.Type: GrantFiled: December 13, 2021Date of Patent: September 3, 2024Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, Kabushiki Kaisha Takai Rika Denki SeisakushoInventors: Yuya Goto, Naoyuki Takada, Kosuke Taki, Daisuke Ogawa, Hirokazu Itakura, Takahiko Ando
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Patent number: 10553674Abstract: A substrate for semiconductor device includes a substrate, a buffer layer which is provided on the substrate and made of a nitride semiconductor, and a device active layer which is provided on the buffer layer and composed of a nitride semiconductor layer, wherein the buffer layer contains carbon and iron, a carbon concentration of an upper surface of the buffer layer is higher than a carbon concentration of a lower surface of the buffer layer, and an iron concentration of the upper surface of the buffer layer is lower than an iron concentration of the lower surface of the buffer layer. As a result, the substrate for semiconductor device can reduce a leak current in a lateral direction at the time of a high-temperature operation while suppressing a leak current in a longitudinal direction.Type: GrantFiled: June 17, 2016Date of Patent: February 4, 2020Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
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Patent number: 10319587Abstract: A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.Type: GrantFiled: February 10, 2015Date of Patent: June 11, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi, Shoichi Kobayashi, Hirotaka Kurimoto
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Patent number: 10189670Abstract: A paper sheet handling machine (for example, a banknote handling machine (10)) includes: a storage unit (for example, an escrow unit (20), banknote storages (30), a banknote storage cassette (40)) configured to store a paper sheet transported from a transport unit (16); and a shifting unit (19) provided in the transport unit (16) and configured to shift the paper sheet transported by the transport unit (16), in a width direction orthogonal to a direction in which the paper sheet is transported, according to a position, in the width direction, of a specific member (for example, a tape (136) in the escrow unit (20), a pair of feed rollers of a banknote feeding mechanism (32, 42) provided in the banknote storages (30), a banknote storage cassette (40)) in the storage unit.Type: GrantFiled: February 8, 2016Date of Patent: January 29, 2019Assignee: GLORY LTD.Inventors: Takeshi Yokawa, Kazuaki Nishimura, Hirokazu Goto
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Patent number: 10133524Abstract: An electronic apparatus includes circuitry and a wireless communication device. The circuitry controls the electronic apparatus to transition between a first power mode in which the electronic apparatus performs predetermined functions, and a second power mode in which the electronic apparatus consumes power less than that of the first power mode. The wireless communication device outputs a notification signal via a short-range wireless communication when the electronic apparatus is in the second power mode, and outputs a return request signal in response to a connection request signal transmitted from an external device that has received the notification signal to establish a short-range wireless communication connection with the external device. The circuitry causes the electronic apparatus to transition from the second power mode to the first power mode when the wireless communication device outputs the return request signal.Type: GrantFiled: June 22, 2017Date of Patent: November 20, 2018Assignee: Ricoh Company, Ltd.Inventor: Hirokazu Goto
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Patent number: 10115589Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.Type: GrantFiled: December 18, 2015Date of Patent: October 30, 2018Assignees: SHIN-ETSU HANDOTAI CO., LTD., SANKEN ELECTRIC CO., LTD.Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi
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Patent number: 10068985Abstract: A method for manufacturing a semiconductor substrate, the semiconductor substrate including: a substrate; an initial layer provided on the substrate; a high-resistance layer provided on the initial layer which is composed of a nitride-based semiconductor and contains carbon; and a channel layer provided on the high-resistance layer which is composed of a nitride-based semiconductor, and at a step of forming the high-resistance layer, a gradient is given to a preset temperature at which the semiconductor substrate is heated, and the high-resistance layer is formed such that the preset temperature at the start of formation of the high-resistance layer is different from the preset temperature at the end of formation of the high-resistance layer. It is possible to provide the method for manufacturing a semiconductor substrate, which can reduce a concentration gradient of carbon concentration in the high-resistance layer and also provide a desired value for the carbon concentration.Type: GrantFiled: March 5, 2015Date of Patent: September 4, 2018Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
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Publication number: 20180245240Abstract: A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.Type: ApplicationFiled: February 22, 2018Publication date: August 30, 2018Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Kazunori HAGIMOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Hirokazu GOTO, Ken SATO, Hiroshi SHIKAUCHI, Shoichi KOBAYASHI, Hirotaka KURIMOTO
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Publication number: 20180204908Abstract: A substrate for semiconductor device includes a substrate, a buffer layer which is provided on the substrate and made of a nitride semiconductor, and a device active layer which is provided on the buffer layer and composed of a nitride semiconductor layer, wherein the buffer layer contains carbon and iron, a carbon concentration of an upper surface of the buffer layer is higher than a carbon concentration of a lower surface of the buffer layer, and an iron concentration of the upper surface of the buffer layer is lower than an iron concentration of the lower surface of the buffer layer. As a result, the substrate for semiconductor device can reduce a leak current in a lateral direction at the time of a high-temperature operation while suppressing a leak current in a longitudinal direction.Type: ApplicationFiled: June 17, 2016Publication date: July 19, 2018Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
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Patent number: 9966259Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/cm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.Type: GrantFiled: May 3, 2017Date of Patent: May 8, 2018Assignees: SHANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
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Patent number: 9938638Abstract: A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.Type: GrantFiled: February 10, 2015Date of Patent: April 10, 2018Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Kazunori Hagimoto, Masaru Shinomiya, Keitaro Tsuchiya, Hirokazu Goto, Ken Sato, Hiroshi Shikauchi, Shoichi Kobayashi, Hirotaka Kurimoto
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Publication number: 20180057302Abstract: A paper sheet handling machine (for example, a banknote handling machine (10)) includes: a storage unit (for example, an escrow unit (20), banknote storages (30), a banknote storage cassette (40)) configured to store a paper sheet transported from a transport unit (16); and a shifting unit (19) provided in the transport unit (16) and configured to shift the paper sheet transported by the transport unit (16), in a width direction orthogonal to a direction in which the paper sheet is transported, according to a position, in the width direction, of a specific member (for example, a tape (136) in the escrow unit (20), a pair of feed rollers of a banknote feeding mechanism (32, 42) provided in the banknote storages (30), a banknote storage cassette (40)) in the storage unit.Type: ApplicationFiled: February 8, 2016Publication date: March 1, 2018Inventors: Takeshi YOKAWA, Kazuaki NISHIMURA, Hirokazu GOTO
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Publication number: 20180032291Abstract: An electronic apparatus includes circuitry and a wireless communication device. The circuitry controls the electronic apparatus to transition between a first power mode in which the electronic apparatus performs predetermined functions, and a second power mode in which the electronic apparatus consumes power less than that of the first power mode. The wireless communication device outputs a notification signal via a short-range wireless communication when the electronic apparatus is in the second power mode, and outputs a return request signal in response to a connection request signal transmitted from an external device that has received the notification signal to establish a short-range wireless communication connection with the external device. The circuitry causes the electronic apparatus to transition from the second power mode to the first power mode when the wireless communication device outputs the return request signal.Type: ApplicationFiled: June 22, 2017Publication date: February 1, 2018Applicant: Ricoh Company, Ltd.Inventor: Hirokazu GOTO
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Patent number: 9876101Abstract: A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region.Type: GrantFiled: March 12, 2015Date of Patent: January 23, 2018Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTDInventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Kazunori Hagimoto, Keitaro Tsuchiya
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Publication number: 20170352537Abstract: An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.Type: ApplicationFiled: December 18, 2015Publication date: December 7, 2017Applicants: SHIN-ETSU HANDOTAI CO., LTD., SANKEN ELECTRIC CO., LTD.Inventors: Kazunori HAGIMOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Hirokazu GOTO, Ken SATO, Hiroshi SHIKAUCHI
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Publication number: 20170323960Abstract: An epitaxial wafer including: a silicon-based substrate; a first buffer layer on the substrate and including a first multilayer structure buffer region composed of AlxGa1-xN layers and AlyGa1-yN layers (x>y) alternately disposed and a first insertion layer composed of an AlzGa1-zN layer (x>z) and is thicker than the AlyGa1-yN layer, the first regions and insertion layers alternately disposed; a second buffer layer on the first and including a second multilayer structure buffer region composed of Al?Ga1-?N layers and Al?Ga1-?N layers (?>?) alternately disposed and a second insertion layer composed of an Al?Ga1-?N layer (?>?) and is thicker than the Al?Ga1-?N layer, the second regions and insertion layers alternately disposed; and a channel layer on the second buffer layer and thicker than the second insertion layer. The average Al composition in the second buffer layer is higher than that in the first.Type: ApplicationFiled: November 6, 2015Publication date: November 9, 2017Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
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Publication number: 20170236711Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/cm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO. LTD.Inventors: Hiroshi SHIKAUCHI, Ken SATO, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO
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Patent number: 9673052Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/atomscm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.Type: GrantFiled: May 2, 2014Date of Patent: June 6, 2017Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
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Publication number: 20170133217Abstract: A semiconductor substrate including: substrate; buffer layer provided on substrate; high-resistance layer provided on buffer layer, high-resistance layer being composed of nitride-based semiconductor and containing transition metal and carbon; and channel layer provided on high-resistance layer, channel layer being composed of nitride-based semiconductor, wherein high-resistance layer includes reduction layer in contact with channel layer, reduction layer being layer in which concentration of transition metal is reduced from side where buffer layer is located toward side where channel layer is located, and reduction rate at which carbon concentration is reduced toward channel layer is higher than reduction rate at which concentration of transition metal is reduced toward channel layer.Type: ApplicationFiled: March 5, 2015Publication date: May 11, 2017Applicants: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.Inventors: Ken SATO, Hiroshi SHIKAUCHI, Hirokazu GOTO, Masaru SHINOMIYA, Keitaro TSUCHIYA, Kazunori HAGIMOTO