Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

Abstract: An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.

Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

Abstract: An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.

Abstract: The number of pulses of an operation clock to a microprocessor can be easily and instantaneously controlled and changed, in which a clock control device 2 supplies a clock of the same pulse number as the system clock 8, while a bus busy signal 10 that indicates a bus 4 is in a busy state from a microprocessor 1 is existing, and supplies a clock having random gap of a reduced number of pulses of the system clock 8, while the bus busy signal 10 is not existing, respectively to the microprocessor 1 as operation clock.

Abstract: A signal processor for pipeline processing which can effectively avoid deterioration of the processing efficiency caused by branch instructions and methods thereof: wherein when obtaining a result that an instruction decoded in an ID module is a branch instruction, determination is made as to branch existence in an EX module in the next cycle, and an instruction in a branch destination and an instruction in a non-branch destination are fetched simultaneously in an IF module; consequently, in the next cycle, in response to the result of the branch existence, one of the fetched instructions of the branch destination or the non-branch destination is selected and is then decoded in an ID module.