Patents by Inventor Hirokazu Harima

Hirokazu Harima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220385766
    Abstract: A multiple dwelling house interphone system includes a communication management device that controls communication between the collective entrance machine and the mobile phone. The communication management device relays the communication to the mobile phone registered as a calling destination of the collective entrance machine to be linked to the dwelling room master device using a predetermined application based on a VOIP. When a predetermined registration operation to allow communication with the communication management device based on the VOIP is performed to link the mobile phone to the dwelling room master device, information list on mobile phones already registered relative to the dwelling room master device as a link target is transmitted from the communication management device having accepted the registration in addition to an application for a download, and the mobile phone that has downloaded the application displays the information list on a display section of the mobile phone.
    Type: Application
    Filed: March 23, 2022
    Publication date: December 1, 2022
    Applicant: Aiphone Co., Ltd.
    Inventors: Hirokazu HARIMA, Hiroki KOTO, Kimiaki FUJISHIMA, Ryoji UNO
  • Patent number: 4729063
    Abstract: A plastic molded semiconductor integrated circuit device, includes: a semiconductor substrate in which circuit elements are fabricated, metal wirings for transmitting the power supply voltage or signals of internal circuits provided on the semiconductor substrate via an insulating film, a plurality of apertures produced at portions of the insulating film directly below the metal wirings, and a nail section provided integrally with the metal wiring in the aperture, wherein the nail section is provided without being electrically connected with any of the circuit elements or the other metal wirings.
    Type: Grant
    Filed: February 20, 1986
    Date of Patent: March 1, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ryuichi Matsuo, Masahide Kaneko, Hirokazu Harima
  • Patent number: 4651186
    Abstract: A field effect transistor comprises a source region (42) annularly formed to encompass and spaced apart from a drain region (41), whereby a second channel region is formed between the drain region and the source region in the vicinity of the former, while a first channel region is formed in the remaining area thereof, an annular first gate (43) formed bridging above the first channel region and the source region, a second annular gate (45) formed bridging above the first gate and the drain region, and an isolating film (47) formed contiguous to the source region at the side opposite to the channel region. As a result any region is eliminated where the channel region in the vicinity of the drain side end of the first gate (43) is in contact with the isolating film (47). Accordingly, no withstand voltage is restricted thereby and the withstand voltage of the field effect transistor is considerably enhanced.
    Type: Grant
    Filed: November 1, 1982
    Date of Patent: March 17, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Makoto Yamamoto, Tsuyoshi Toyama, Hirokazu Harima, Ryo Ando