Abstract: An electronic device comprises memory pillars comprising a channel material. The memory pillars extend through both a cell region and a lateral contact region. A portion of the memory pillars in the lateral contact region comprise at least one first step and at least one second step. The electronic device comprises a source contact in direct contact with the channel material in the at least one second step of the portion of the memory pillars in the lateral contact region. Additional electronic devices and methods of forming an electronic device are also disclosed.

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, and a columnar portion. The stacked body, provided on the substrate, includes first conductive layers and first insulating layers provided alternately along a first direction. The columnar portion extends through the stacked body in the first direction. The columnar portion includes a blocking layer, a charge storage layer, a tunneling layer, and a semiconductor layer. The columnar portion includes a first portion and a second portion. The second portion is provided on the substrate side of the first portion. A dimension in the second direction of the second portion is smaller than a dimension in a second direction of the first portion. A portion of the blocking layer is provided at the second portion being thicker than a portion of the blocking layer provided at the first portion.

Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, and a columnar portion. The stacked body, provided on the substrate, includes first conductive layers and first insulating layers provided alternately along a first direction. The columnar portion extends through the stacked body in the first direction. The columnar portion includes a blocking layer, a charge storage layer, a tunneling layer, and a semiconductor layer. The columnar portion includes a first portion and a second portion. The second portion is provided on the substrate side of the first portion. A dimension in the second direction of the second portion is smaller than a dimension in a second direction of the first portion. A portion of the blocking layer is provided at the second portion being thicker than a portion of the blocking layer provided at the first portion.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.

Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.

Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.

Abstract: According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.

Abstract: A nonvolatile semiconductor storage device includes a stack structure including first insulating films and first electrode films stacked alternately, the stack structure having a first through hole extending therethrough; a second electrode film provided above the stack structure, the second electrode film having a second through hole extending therethrough and communicating with the first through hole; a second insulating film provided above the second electrode film and having a third through hole extending therethrough and communicating with the second through hole; a semiconductor film provided along inner surfaces of the first and the second through holes; a memory film provided between the first electrode film and the semiconductor film; and a gate insulating film provided between the second electrode film and the semiconductor film; the third through hole becoming narrower toward an upper side of the stack direction and wider toward a lower side of a stack direction.

Abstract: A semiconductor memory device according to an embodiment includes a stacked body with electrode films and inter-electrode insulating films alternately stacked therein, a semiconductor member, a charge accumulation film, an insulating member and a floating electrode member. The semiconductor member is provided in the stacked body. The insulating member is provided at a position opposed to the inter-electrode insulating film on a side surface of the charge accumulation film. The insulating member is divided for each of the inter-electrode insulating films. The floating electrode member is provided on a region of the side surface of the charge accumulation film not covered with the insulating member. The floating electrode member is in contact with the charge accumulation film. The floating electrode member is divided for each of the electrode films. The floating electrode member has higher conductivity than the charge accumulation film.

Abstract: A semiconductor memory device according to an embodiment includes a stacked body with electrode films and inter-electrode insulating films alternately stacked therein, a semiconductor member, a charge accumulation film, an insulating member and a floating electrode member. The semiconductor member is provided in the stacked body. The insulating member is provided at a position opposed to the inter-electrode insulating film on a side surface of the charge accumulation film. The insulating member is divided for each of the inter-electrode insulating films. The floating electrode member is provided on a region of the side surface of the charge accumulation film not covered with the insulating member. The floating electrode member is in contact with the charge accumulation film. The floating electrode member is divided for each of the electrode films. The floating electrode member has higher conductivity than the charge accumulation film.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body having a plurality of electrode layers containing boron and silicon, and a plurality of insulating layers each provided between the electrode layers; a channel body penetrating through the stacked body; and a memory film provided between the channel body and each of the electrode layer. The memory film includes a tunnel film, a charge storage film, and a block film, provided in order from the channel body side. The block film includes a silicon nitride film, and a first silicon oxide film provided between the silicon nitride film and the electrode layer and being in contact with the electrode layer.

Abstract: A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a state storage element and a transistor. In the state storage element, a first conductive region, a first insulating film, and a first electrode are successively formed on a semiconductor substrate. Further, a second insulating film and a second electrode are successively formed on the semiconductor substrate. The transistor includes the first conductive region, a second conductive region, a second insulating film, and a second electrode. The second insulating film and the second electrode are successively formed between the first and second conductive regions on the semiconductor substrate. The withstand voltage against dielectric breakdown of the first insulating film is lower than that of the second insulating film.

Abstract: A semiconductor device includes a plurality of metal insulator semiconductor (MIS) transistors. The plurality of MIS transistors each includes a gate electrode formed above a channel region of a semiconductor substrate via a gate insulating film and source/drain regions formed on both sides of the channel region. The gate electrode is electrically connected to an interconnect via a first plug. The interconnect has a plurality of vias formed thereon. The plurality of MIS transistors have threshold voltages different from one another due to variations in quantities of electric charges trapped by the gate insulating films respectively corresponding to the plurality of MIS transistors.

Abstract: The present invention provides an annealing apparatus including a heating unit, a storage unit, a calculating unit, and a control unit. The heating unit anneals a target wafer. The storage unit stores reference data which a shape parameter of a reference element, an annealing temperature, and an electrical characteristic of the reference element are associated with one another. The reference data is obtained by measuring a wafer previously manufactured. The calculating unit determines an actual annealing temperature based on the reference data and measurement data to attain target electrical characteristic. The measurement data include a shape parameter of an element formed in the target wafer. The control unit controls the heating unit to anneal the target wafer at the actual annealing temperature.