Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a–40e, 41a–41e and 42a–42d), a plurality of LEADs (50a–50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a–60e and 61a–61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a–40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a–50d).

Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a-40e, 41a-41e and 42a-42d), a plurality of LEADs (50a-50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a-60e and 61a-61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a-40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a-50d).

Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a-40e, 41a-41e and 42a-42d), a plurality of LEADs (50a-50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a-60e and 61a-61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a-40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a-50d).

Abstract: A plurality of for-wafer-test input/output elements exclusively used in a wafer test are arranged with a plurality of input/output ports corresponding to a plurality of internal circuits in a semiconductor integrated circuit. In the wafer test, a probe is connected with each for-wafer-test input/output element, input test signals are input from an external apparatus to the input/output ports through one for-wafer-test input/output element connected with the probe and are sent to the internal circuits. Thereafter, output test signals obtained in the internal circuits are read out to the input/output ports and are output from the input/output ports to another external apparatus through another for-wafer-test input/output element connected with the probe, so that functions of the internal circuits can be checked.