Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.

Abstract: A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.

Abstract: A high electron mobility transitor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

Abstract: Lower metal wiring is formed on a base insulating film. A BCB film which is formed of a BCB (benzocyclobutene) resin is formed on the base insulating film and metal wiring. A SiO2 film is formed on the BCB film. A resist film is formed on the SiO2 film, and patterned using a lithography technique. The SiO2 film is etched using the resist film as a mask. The BCB film is anisotropically etched with a mixture of Cl2/BCl3/O2 using the SiO2 film as a mask, thereby to form a contact hole. The contact hole is filled with a conductor, thereby forming upper metal wiring.

Abstract: A high electron mobility transistor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

Abstract: In a method of manufacturing a semiconductor device which has a semiconductor substrate, a channel layer formed on the semiconductor substrate and an insulating film deposited on the channel layer, an opening corresponding to a gate electrode pattern is formed in the insulating film by the use of a photoresist film. The channel layer contains crystal components while the photo-resist film contains carbon. The insulating film is etched to exposed said channel layer after removing the photoresist film. In consequence, no reacted production is formed between the crystal components and the carbon on the exposed channel layer.

Abstract: On a semiconductor substrate, a channel layer, an electron supply layer, a third semiconductor layer, a second etching stopper layer, a second semiconductor layer and a first etching stopper layer and a first semiconductor layer are grown in sequential order to form E-type and D-type FETs. The third semiconductor layer and the second semiconductor layer have equal layer thickness, and the second etching stopper layer and the first etching stopper layer have the equal layer thickness. Thus, Vth of the E-type and D-type FETs can be controlled at the predetermined value with high reproduction ability.

Abstract: Disclosed is a method selective of vapor phase etching for fabricating a semiconductor device having a refractory metal silicide electrode abutting a silicon oxide film on the surface or a semiconductor device having an AlGaAs layer, an electrode formed on the AlGaAs layer and a silicon oxide film on the surface of the semiconductor device. The method comprises a step of removing a portion of the silicon oxide film by a gas including a vapor of hydrogen fluoride. The method further uses a mixture of nitrogen gas including vapor of anhydrous hydrofluoric acid and a nitrogen gas including a vapor of H.sub.2 O, wherein the ratio of the nitrogen gas including the vaporized anhydrous hydrofluoric acid to the nitrogen gas including vapor of H.sub.2 O is less than 1.

Abstract: After forming a silicon oxide layer and an amorphous silicon layer on a GaAs substrate in stacking manner, a gate electrode forming opening portion is formed by RIE etching. Then, by selectively removing only the amorphous silicon layer at the portion contacting with the opening portion at the side of the source electrode, a WSi.cndot.TiN.cndot.Pt layer is formed within the opening portion. Subsequently, after applying an organic photoresist layer, an entire surface is etched back to remove at least the WSi.cndot.TiN.cndot.Pt layer above the amorphous silicon layer. Then, by using the WSi.cndot.TiN.cndot.Pt layer remaining in the opening portion as a plating electrode, an Au layer is plated to form a reversed L-shaped gate electrode with an overhanging portion only extending toward the source electrode.