Abstract: According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.

Abstract: According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.

Abstract: A semiconductor integrated circuit device is disclosed, which incorporates a mask ROM of a contact program scheme in which a drain contact of each of transistors which constitute a memory cell array is connected to a bit line through an interconnecting pattern and a via plug, wherein a plurality of via plugs are connected to a same bit line and continuously adjacently arranged in a bit line direction, a plurality of interconnecting patterns are arranged in association with the plurality of via plugs, and at least two continuously adjacent via plugs of the plurality of via plugs are commonly connected to each other by a common connecting wiring layer extending in the bit line direction through the interconnecting patterns in association with the at least two adjacent via plugs.

Abstract: A semiconductor integrated circuit is a synchronous semiconductor integrated circuit which operates in synchronism with a clock signal, and includes memory cells, bit lines, a pre-charge circuit and a pre-charge controlling circuit. The memory cells store information, and are connected to the bit lines. The pre-charge circuit performs a pre-charge operation for pre-charging a bit line. The pre-charge controlling circuit controls the pre-charge operation of the pre-charge circuit. The pre-charge controlling circuit synchronizes starting of the pre-charge operation with the edge of the clock signal.

Abstract: A portion of an image is selected as an arbitrary rectangle indicated by diagonal coordinates, and this portion of an image is encrypted and embedded in the original rectangular image portion, thus accomplishing partial encryption of the image. This is done by an image encryption device, in which an partial image data selector, encryptor and decryptor are connected via a memory; and a display, auxiliary (external) memory, keyboard, mouse, image scanner, camera, etc. are also connected. At the time of decryption, the encrypted rectangle is decrypted and returned to its original state.

Abstract: An information processing system using error-correcting codes and/or cryptography for processing and transmitting data including documents, drawings, images, and data bases includes a mechanism by which optional portions of data can be selected on a display screen and be assigned reliability and/or security levels, making possible the setting of access authority levels for optional portions of data. All or each optional portion of data within items or files can be processed and enciphered. Cipher text can be displayed on a screen. Then a security system being superior to man-machine interface is provided. For example, a company president can thus access secret data without that data being accessible to information managers and secretaries.