Abstract: A mirror unit 2 includes a mirror device 20 including a base 21 and a movable mirror 22, an optical function member 13, and a fixed mirror 16 that is disposed on a side opposite to the mirror device 20 with respect to the optical function member 13. The mirror device 20 is provided with a light passage portion 24 that constitutes a first portion of an optical path between the beam splitter unit 3 and the fixed mirror 16. The optical function member 13 is provided with a light transmitting portion 14 that constitutes a second portion of the optical path between the beam splitter unit 3 and the fixed mirror 16. A second surface 21b of the base 21 and a third surface 13a of the optical function member 13 are joined to each other.

Abstract: A controller assembly includes a base plate, a bracket, and a first controller main body. The base plate includes a through hole and a frame having an upper surface and a lower surface and surrounding the through hole. The bracket has first and second flange portions supported on the upper surface of the frame at positions opposite to each other over the through hole, first and second side portions coupled respectively to the first and second flange portions and passing through the though hole; and a bottom portion coupled to both of the first and second side portions on the side of the lower surface of the frame. The first controller main body is mounted on a bottom portion of the bracket. Accordingly, a controller assembly which can be readily assembled, a cab of a work implement, and a work machine can be obtained.

Abstract: A controller assembly includes a base plate, a bracket, and a first controller main body. The base plate includes a through hole and a frame having an upper surface and a lower surface and surrounding the through hole. The bracket has first and second flange portions supported on the upper surface of the frame at positions opposite to each other over the through hole, first and second side portions coupled respectively to the first and second flange portions and passing through the though hole; and a bottom portion coupled to both of the first and second side portions on the side of the lower surface of the frame. The first controller main body is mounted on a bottom portion of the bracket. Accordingly, a controller assembly which can be readily assembled, a cab of a work implement, and a work machine can be obtained.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: A cab for a construction machine includes hinges that swingably mount the door to the wall. Each of the hinges includes a first member secured to a first cut-out portion of the wall, a second member secured to a second cut-out portion of the door, an interposed member interposed between the first and second members, and first and second pivot shafts pivotally respectively coupling the first and second members to the interposed member. The cab further includes first and second stoppers that regulate first and second angles of the interposed member with respect to the first and second members, respectively, and a bolt member arranged in the second stopper to move in its axial direction to adjust the second angle. An imaginary surface corresponding to an outermost part of each of the hinges is substantially coplanar with exterior surfaces of the wall and the door, when the door is closed.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: A cab for a construction machine includes hinges that swingably mount the door to the wall. Each of the hinges includes a first member secured to a first cut-out portion of the wall, a second member secured to a second cut-out portion of the door, an interposed member interposed between the first and second members, and first and second pivot shafts pivotally respectively coupling the first and second members to the interposed member. The cab further includes first and second stoppers that regulate first and second angles of the interposed member with respect to the first and second members, respectively, and a bolt member arranged in the second stopper to move in its axial direction to adjust the second angle. An imaginary surface corresponding to an outermost part of each of the hinges is substantially coplanar with exterior surfaces of the wall and the door, when the door is closed.

Abstract: The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: In a signal receiving circuit there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. The selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: A data transmission circuit transmits transmission data to a receiving apparatus. The clock transmission circuit transmits a transmission clock to the receiving apparatus when the transmission data is transmitted by the data transmission circuit. The phase control circuit varies a phase of the transmission clock to a phase different from that of the transmission data after the transmission clock is transmitted from the clock transmission circuit.

Abstract: The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.

Abstract: In a signal receiving circuit including a plurality of input channels, there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. If one of the input detection circuits 2a to 2n detects the input of the signal of the corresponding channel, the selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels.

Abstract: A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Abstract: A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly.

Abstract: A synchronization circuit comprises a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock; a delay selection circuit for adding a delay to the input signal on the basis of the control signal; and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Abstract: A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

Abstract: In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.