Abstract: A test pattern generating apparatus generates a test pattern for evaluating whether or not source data and a bit synchronous clock signal SCK are transmitted normally through a bus connecting a plurality of terminal units for transmitting and receiving source data. A test pattern generating circuit 33 generates predetermined test pattern data which are predetermined as the test pattern, based on the bit synchronous clock signal and a frame synchronous clock signal LRCK and outputs the test pattern data, bit synchronous clock signal and frame synchronous clock signal to the bus.

Abstract: The object of the present invention is to provide a data transmission system, wherein even when more than two among a plurality of stations interconnected by one common transmission line try to communicate mutually by a start-stop transmission PWM mode, if the phases within a bit in the data of the own station and a corresponding bit of the data on the transmission line which has been received through a plurality of own station are compared and they coincide with each other as the result thereof, then the own station continues transmitting the data, while otherwise it comes to stop transmitting, whereby even if there is a difference between the clock frequency of the own station and that of another station, the phases in the corresponding bits of the two different data can be smoothly compared.