Patents by Inventor Hirokazu Uemura

Hirokazu Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080088885
    Abstract: A data printing system. In a data processing apparatus, a transmission converting unit converts electronic data into print data, a data transmitting unit transmits converted print data to a printer apparatus, a transmission confirming unit detects alteration of printed electronic data, and an alarm providing unit provides predetermined alarm data to print data to be transmitted when an alteration is detected. In the printer apparatus, a data receiving unit receives print data from the data processing apparatus, a data printing unit prints received print data, an alarm detecting unit detects alarm data provided on received print data, and an alarm reporting unit reports an alteration alarm when alarm data is detected.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 17, 2008
    Applicant: MURATA MACHINERY, LTD.
    Inventors: Jinichi MIYAZAKI, Hirokazu UEMURA
  • Patent number: 6691296
    Abstract: A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: February 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Nakayama, Yukihiro Fukumoto, Yoshiyuki Saito, Hirokazu Uemura
  • Patent number: 6629302
    Abstract: A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 30, 2003
    Inventors: Shinji Miura, Yukihiro Fukumoto, Hirokazu Uemura, Yoshiyuki Saito, Hiroshi Ikeda, Takeshi Nakayama, Osamu Shibata, Shinichi Tanimoto
  • Publication number: 20010047508
    Abstract: A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.
    Type: Application
    Filed: December 22, 2000
    Publication date: November 29, 2001
    Inventors: Shinji Miura, Yukihiro Fukumoto, Hirokazu Uemura, Yoshiyuki Saito, Hiroshi Ikeda, Takeshi Nakayama, Osamu Shibata, Shinichi Tanimoto
  • Patent number: 5847968
    Abstract: When a component is placed on a circuit board, a placement position is determined by method of elastic center. Then, it is determined whether the component was placed on the circuit board. After that, connectors are routed between the component and a design candidate component which is already placed. After that, the next component is set, and the above mentioned packaging processing is repeated.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: December 8, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinji Miura, Masayuki Tsuchida, Hirokazu Uemura, Hiroyuki Yoshimura, Yuichi Nishimura
  • Patent number: 5691913
    Abstract: A layout designing apparatus for circuit boards including a mother board and a substrate which comprises a layout data storage unit for having areas to store data; an operation unit for giving directions; a mother board setting unit for creating the data about the mother board in the layout data storage unit according to the operation unit; a substrate placement unit for creating the data in the layout data storage unit according to the operation unit so that the substrate of a given configuration is placed on a given place on the mother board; a component placement unit for creating the data in the layout data storage unit according to the operation unit so that components of given configurations are placed on given places on the mother board and on the substrate; a routing unit for creating the data in the layout data storage unit according to the operation unit so that routing paths of given configurations are laid out on the mother board and on the substrate; a display unit; and a layout data display cont
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: November 25, 1997
    Assignee: Matsushita Electric Ind. Co.
    Inventors: Masayuki Tsuchida, Yukinobu Nishikawa, Hirokazu Uemura, Shinji Miura
  • Patent number: 5559997
    Abstract: According to the printed-circuit board of the preset invention, the circuit modification unit 120 adds a noise reduction component, based on circuit board information inputted to the design information input unit 106. Then, the layout unit 132 sets a layout after the design rule generation unit 133 generates a design rule. The rated value modification unit 124 determines rated values of noise reduction components in accordance with the layout. Thus, design rule generation, noise reduction component addition, and rated value determination are automatically performed to satisfy the electric characteristics of evaluation targets. Consequently, interactive process in designing is reduced and the efficiency of designing can be realized.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: September 24, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masayuki Tsuchida, Hirokazu Uemura, Shinji Miura, Yoshiyuki Saito, Hiroyuki Yoshimura, Yuichi Nishimura, Nobuo Sueda