Patents by Inventor Hirokazu Yonezawa
Hirokazu Yonezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7308381Abstract: Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.Type: GrantFiled: July 31, 2006Date of Patent: December 11, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7239997Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.Type: GrantFiled: January 14, 2004Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7222319Abstract: A timing analysis apparatus reads a net list including connection information and the like of circuit cells of an LSI, delay data for previously storing delay information of the circuit cells, stage count-derating factor dependency and components P, V and T of a derating factor; detects the number of stages of each signal path by a signal path cell counting section; determines a derating factor corresponding to the extent of averaging of random variation of each signal path in accordance with the number of stages of the signal path; and performs timing analysis on the basis of the determined derating factor. Therefore, more realistic and highly accurate timing design can be performed on a large-scale circuit.Type: GrantFiled: April 8, 2005Date of Patent: May 22, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7197728Abstract: After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.Type: GrantFiled: June 17, 2004Date of Patent: March 27, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Publication number: 20070050742Abstract: Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.Type: ApplicationFiled: July 31, 2006Publication date: March 1, 2007Inventor: Hirokazu Yonezawa
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Publication number: 20060107244Abstract: A total random number sequence generator generates a total random number sequence of an entire circuit, as fabrication variation. A signal path random number sequence extracting section extracts, from the total random number sequence, a signal path random number sequence for a partial circuit obtained by dividing the entire circuit. A circuit simulating section executes Monte Carlo analysis using the signal path random number sequence for each partial circuit, thereby obtaining a desired circuit characteristic distribution. In this manner, correlation is maintained between divided circuit characteristic distributions and, in addition, the obtained circuit characteristic distribution is used for clock skew distribution calculation and others. Moreover, the circuit scale of a target of circuit simulation is reduced.Type: ApplicationFiled: August 23, 2005Publication date: May 18, 2006Inventor: Hirokazu Yonezawa
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Publication number: 20050276135Abstract: A timing analysis apparatus reads a net list including connection information and the like of circuit cells of an LSI, delay data for previously storing delay information of the circuit cells, stage count-derating factor dependency and components P, V and T of a derating factor; detects the number of stages of each signal path by a signal path cell counting section; determines a derating factor corresponding to the extent of averaging of random variation of each signal path in accordance with the number of stages of the signal path; and performs timing analysis on the basis of the determined derating factor. Therefore, more realistic and highly accurate timing design can be performed on a large-scale circuit.Type: ApplicationFiled: April 8, 2005Publication date: December 15, 2005Inventor: Hirokazu Yonezawa
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Publication number: 20050177356Abstract: Variables corresponding to a plurality of fabrication variation components per parameter out of parameters included in input information are incorporated in accordance with a given model. Fabrication variation of the parameter is obtained by selectively giving fabrication variation information of respective fabrication variation components to the variables corresponding to the plurality of fabrication variation components by using the model, and input information influenced by the fabrication variation is output. In accordance with the output, circuit simulation is executed by referring to the input information influenced by the fabrication variation of the parameter.Type: ApplicationFiled: November 3, 2004Publication date: August 11, 2005Inventor: Hirokazu Yonezawa
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Patent number: 6869808Abstract: There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The property (delay) of a circuit A (ring oscillator) in a wafer or mounted chip is measured actually or simulated and the property of a circuit B (LSI) is simulated. Then, the interrelation between the degree of property degradation of the circuit A and the degree of property degradation of the circuit B is determined. The circuit property of a circuit AA (ring oscillator) having substantially the same degree of property degradation as the circuit A and manufactured under a new manufacturing condition is measured actually or simulated so that the degree of property degradation of a circuit BB is predicted from the interrelation and the degree of property degradation of the circuit AA.Type: GrantFiled: July 31, 2002Date of Patent: March 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokazu Yonezawa, Satoshi Ishikura
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Publication number: 20040261044Abstract: After predicting the relationship between a design margin set against fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated.Type: ApplicationFiled: June 17, 2004Publication date: December 23, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO. LTDInventor: Hirokazu Yonezawa
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Patent number: 6795802Abstract: The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305.Type: GrantFiled: March 19, 2001Date of Patent: September 21, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokazu Yonezawa, Yoshiyuki Kawakami, Nobufusa Iwanishi
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Publication number: 20040167756Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.Type: ApplicationFiled: January 14, 2004Publication date: August 26, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Hirokazu Yonezawa
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Publication number: 20030054577Abstract: There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The property (delay) of a circuit A (ring oscillator) in a wafer or mounted chip is measured actually or simulated and the property of a circuit B (LSI) is simulated. Then, the interrelation between the degree of property degradation of the circuit A and the degree of property degradation of the circuit B is determined. The circuit property of a circuit AA (ring oscillator) having substantially the same degree of property degradation as the circuit A and manufactured under a new manufacturing condition is measured actually or simulated so that the degree of property degradation of a circuit BB is predicted from the interrelation and the degree of property degradation of the circuit AA.Type: ApplicationFiled: July 31, 2002Publication date: March 20, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hirokazu Yonezawa, Satoshi Ishikura
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Publication number: 20020022949Abstract: The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part 101 outputs signal path delay information before deterioration 302 and signal path delay deterioration rate information 303 for each signal path, based on LSI design information 301. A delay vs. delay deterioration rate analyzing part 102 outputs delay vs. delay deterioration rate relationship information 304 showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part 103 extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin 305.Type: ApplicationFiled: March 19, 2001Publication date: February 21, 2002Inventors: Hirokazu Yonezawa, Yoshiyuki Kawakami, Nobufusa Iwanishi
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Patent number: 6278964Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.Type: GrantFiled: May 29, 1998Date of Patent: August 21, 2001Assignees: Matsushita Electric Industrial Co., Ltd., BTA Technology Inc.Inventors: Jingkun Fang, Hirokazu Yonezawa, Lifeng Wu, Yoshiyuki Kawakami, Nobufusa Iwanishi, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
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Patent number: 6219630Abstract: A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes the configuration of a transistor portion in the mask layout of a semiconductor circuit so as to generate transistor-portion-configuration data. Transistor-size calculating means calculates an equivalent transistor size based on the transistor-portion-configuration data, such that a drain current in the circuit simulation coincides with the drain current in the actual device. Corrective-capacitance generating means obtains the difference between a gate capacitance in the circuit simulation using the equivalent transistor size and the gate capacitance in the actual device so as to virtually generate a corrective capacitance having a capacitance value corresponding to the obtained difference.Type: GrantFiled: December 2, 1996Date of Patent: April 17, 2001Assignee: Matsushita Electronics CorporationInventors: Hirokazu Yonezawa, Takuya Umeda, Satoshi Ishikura
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Patent number: 5974247Abstract: An apparatus and method of simulating the operation of an LSI after degradation is provided for predicting actual LSI degradation with time at the design stage, so as to prevent the LSI specification from becoming excessively reliable. A reliability library generation device drives a circuit reliability simulator and generates a reliability library which shows the dependence of the property degradation degree of each circuit cell on predetermined operational conditions. A cell delay degradation estimation means estimates the delay degradation degree with time of each circuit cell which composes a target LSI, by referring to the reliability library. An LSI timing degradation estimation means estimates the delay of each circuit cell in the target LSI which has been degraded with time, based on the delay degradation degree of each circuit cell, and generates an after-degradation LSI timing.Type: GrantFiled: August 27, 1997Date of Patent: October 26, 1999Assignee: Matsushita Electronics CorporationInventor: Hirokazu Yonezawa
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Patent number: 5661413Abstract: A data operating circuit in which a logic combinatorial circuit and a transfer gate are built, and a controller for controlling the data operating circuit are disposed. The controller includes a drive unit for applying a drive signal to a gate of an N-channel transistor included in the transfer gate, and a control unit for controlling the operation of the drive unit. The data operating circuit is supplied with a first voltage via a first power supply line, and the controller is supplied with a second voltage that has a higher voltage value than the first voltage. A signal line for transferring an output signal of the data operating circuit to the controller is provided with a level converter for increasing the level of the output signal of the data operating circuit to a level required for the operation of the control unit. As a result, a timing skew of the transfer gate can be retained small while minimizing power consumption of the data operating circuit.Type: GrantFiled: June 5, 1995Date of Patent: August 26, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Tomita, Toshiyuki Shono, Hirokazu Yonezawa
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Patent number: 5475825Abstract: As a TLB (translation look-aside buffer) of a fully associative system is organized, a first CAM (content addressable memory) cell array and a first RAM (random access memory) cell array which together make up one entry are arranged in such a way that they face each other across a control circuit. As a cache memory of a fully associative system is organized, a second CAM cell array and a second RAM cell array which together make up one entry are arranged in such a way that they face each other across the control circuit. Additionally, the second CAM cell array is located next to the first RAM cell array, whereas the second RAM cell array is located next to the first CAM cell array. These four cell arrays make up one section. At the time of a hit in the first CAM cell array, the control circuit enables readout of the first RAM cell array, while it, at the time of a hit of the second CAM cell array, enables readout of the second RAM cell array.Type: GrantFiled: September 29, 1992Date of Patent: December 12, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokazu Yonezawa, Seiji Yamaguchi
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Patent number: 5463751Abstract: A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array.Type: GrantFiled: December 19, 1994Date of Patent: October 31, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokazu Yonezawa, Seiji Yamaguchi