Abstract: A semiconductor memory device comprises a bit line and source line, a first memory cell and first and second transistors connected therebetween, a second memory cell and third and fourth transistors connected therebetween, and first through fifth wirings connected to the first and the second memory cells and gate electrodes of the first to the fourth transistors. At a first timing of a read operation, voltages of the first through third wirings are larger than voltages of the fourth and fifth wirings. At a second timing, voltages of the second and third wirings are larger than voltages of the fourth and fifth wirings. At a third timing, voltages of the fourth and fifth wirings are larger than their voltages at the second timing. At a fourth timing, voltages of the second and third wirings are larger than a voltage of the fourth wiring.

Abstract: A semiconductor storage device includes: a voltage generation circuit configured to generate a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected and a read-pass voltage to be supplied to an adjacent word line; a word line driver configured to, when the read voltage transitions, apply the read voltage to the selected word line with a first kick voltage amount and apply the read-pass voltage to the adjacent word line with a second kick voltage amount; and a control circuit configured to set each of the first kick voltage amount and the second kick voltage amount to a voltage corresponding to an amount of the transition.

Abstract: A semiconductor storage device includes: a voltage generation circuit configured to generate a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected and a read-pass voltage to be supplied to an adjacent word line; a word line driver configured to, when the read voltage transitions, apply the read voltage to the selected word line with a first kick voltage amount and apply the read-pass voltage to the adjacent word line with a second kick voltage amount; and a control circuit configured to set each of the first kick voltage amount and the second kick voltage amount to a voltage corresponding to an amount of the transition.

Abstract: In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a command to stop is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.

Abstract: A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.

Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.

Abstract: A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.

Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.

Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.

Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.

Abstract: According to one embodiment, a semiconductor memory device includes a word line and a driver. The word line coupled to a memory cell. The driver is configured to apply a voltage to the word line. When a voltage applied to the word line is changed from a first voltage to a second voltage, the driver applies a third voltage according to a voltage difference between the first voltage and the second voltage to the word line.

Abstract: According to one embodiment, a semiconductor storage device includes memory cell array including a memory cell, a bit line coupled to the memory cell, a sense circuit coupled to the bit line and being capable of charging the bit line, and a charging circuit, the memory cell array being disposed between the sense circuit and the charging circuit and being capable of charging the bit line.

Abstract: According to one embodiment, a semiconductor storage device includes memory cell array including a memory cell, a bit line coupled to the memory cell, a sense circuit coupled to the bit line and being capable of charging the bit line, and a charging circuit, the memory cell array being disposed between the sense circuit and the charging circuit and being capable of charging the bit line.

Abstract: In one embodiment of the present invention, the processing surface of a substrate having at least a single crystal surface and a dielectric surface is exposed to a first deposition gas containing a source gas and a doping gas to form a first doped thin film on the single crystal surface, whereas supply of the first deposition gas is stopped before a film is formed on the dielectric surface. Next, the processing surface of the substrate is exposed to a second deposition gas containing a source gas and a doping gas to form a second thin film doped with less dopant than the first thin film on the single crystal surface, whereas supply of the second deposition gas is stopped before a film is formed on the dielectric surface. Subsequently, the processing surface of the substrate is exposed to a chlorine-containing gas to be etched.

Abstract: The present invention provides a method for reducing the agglomeration of a Si layer in an SOI substrate, which can prevent the agglomeration of the Si layer from occurring in a heating and temperature-raising process for the Si layer, when heating and temperature-raising the Si layer that is the outermost surface of the SOI substrate and is in an exposed state, and can prevent the agglomeration further without forming a protective film on the SOI substrate. The method for reducing the agglomeration of the Si layer in the SOI substrate is a method of supplying a hydride gas in a heating and temperature-raising process for the Si layer, when heating and temperature-raising the Si layer which is in an exposed state in the SOI substrate that has an insulation layer and the Si layer sequentially stacked on a Si substrate.

Abstract: A dielectric insulating film including HfO or the like is formed by: cleaning a surface of a semiconductor substrate by exposing the substrate surface to a fluorine radical; performing hydrogen termination processing with a fluorine radical or a hydride (SiH4 or the like); sputtering Hf or the like; and then performing oxidation/nitridation. These steps are carried out without exposing the substrate to atmosphere, thereby making it possible to obtain a C-V curve with less hysteresis and realize a MOS-FET having favorable device characteristics.

Abstract: The present invention provides a method for reducing the agglomeration of a Si layer in an SOI substrate, which can prevent the agglomeration of the Si layer from occurring in a heating and temperature-raising process for the Si layer, when heating and temperature-raising the Si layer that is the outermost surface of the SOI substrate and is in an exposed state, and can prevent the agglomeration further without forming a protective film on the SOI substrate. The method for reducing the agglomeration of the Si layer in the SOI substrate is a method of supplying a hydride gas in a heating and temperature-raising process for the Si layer, when heating and temperature-raising the Si layer which is in an exposed state in the SOI substrate that has an insulation layer and the Si layer sequentially stacked on a Si substrate.

Abstract: A dielectric insulating film including HfO or the like is formed by: cleaning a surface of a semiconductor substrate by exposing the substrate surface to a fluorine radical; performing hydrogen termination processing with a fluorine radical or a hydride (SiH4 or the like); sputtering HE or the like; and then performing oxidation/nitridation. These steps are carried out without exposing the substrate to atmosphere, thereby making it possible to obtain a C-V curve with less hysteresis and realize a MOS-FET having favorable device characteristics.

Abstract: This invention presents an ESC mechanism for chucking an object electro-statically on a chucking surface, comprising a stage having a dielectric block of which surface is the chucking surface, and a chucking electrode provided in the dielectric block. A temperature controller is provided with the stage for controlling temperature of the object. A chucking power source to apply voltage to the chucking electrode is provided so that the object is chucked. The chucking surface has concaves of which openings are shut by the chucked object. A heat-exchange gas introduction system that introduces heat-exchange gas into the concaves is provided. The concaves include a heat-exchange concave for promoting heat-exchange between the stage and the object under increased pressure, and a gas-diffusion concave for making the introduced gas diffuse to the heat-exchange concave. The gas-diffusion concave is deeper than the heat-exchange concave.

Abstract: This invention presents an ESC mechanism for chucking an object electro-statically on a chucking surface, comprising a stage having a dielectric block of which surface is the chucking surface, and a chucking electrode provided in the dielectric block. A temperature controller is provided with the stage for controlling temperature of the object. A chucking power source to apply voltage to the chucking electrode is provided so that the object is chucked. The chucking surface has concaves of which openings are shut by the chucked object. A heat-exchange gas introduction system that introduces heat-exchange gas into the concaves is provided. The concaves include a heat-exchange concave for promoting heat-exchange between the stage and the object under increased pressure, and a gas-diffusion concave for making the introduced gas diffuse to the heat-exchange concave. The gas-diffusion concave is deeper than the heat-exchange concave.