Patents by Inventor Hiroki Etou

Hiroki Etou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7554104
    Abstract: A bolt includes a main body and a spring pin. The main body includes a head and a shaft. The spring pin includes a base portion and an end portion. The shaft includes a portion of external thread and a hollow portion. The head includes a top surface and a hole opened in the top surface. The hole is connected to the hollow portion. The base portion is arranged in the hollow potion to move along an axis of the main body. The end portion is arranged in the hole to move along the axis. The spring pin is energized toward a side of the head such that the end portion protrudes beyond the top surface. The end portion is electrically connected to the portion of external thread.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: June 30, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Yoshirou Shimada, Hiroki Etou, Ryou Kashihara
  • Publication number: 20070243057
    Abstract: A bolt includes a main body and a spring pin. The main body includes a head and a shaft. The spring pin includes a base portion and an end portion. The shaft includes a portion of external thread and a hollow portion. The head includes a top surface and a hole opened in the top surface. The hole is connected to the hollow portion. The base portion is arranged in the hollow potion to move along an axis of the main body. The end portion is arranged in the hole to move along the axis. The spring pin is energized toward a side of the head such that the end portion protrudes beyond the top surface. The end portion is electrically connected to the portion of external thread.
    Type: Application
    Filed: March 15, 2007
    Publication date: October 18, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshirou Shimada, Hiroki Etou, Ryou Kashihara
  • Patent number: 7211868
    Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 1, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Hirokazu Fukuda, Hiroki Etou, Kouji Takahashi
  • Patent number: 6967139
    Abstract: In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: November 22, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Makoto Oikawa, Hiroki Etou, Hirotoshi Kubo, Shouji Miyahara
  • Publication number: 20050029588
    Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET, and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.
    Type: Application
    Filed: September 15, 2004
    Publication date: February 10, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Hirokazu Fukuda, Hiroki Etou, Kouji Takahashi
  • Publication number: 20040256667
    Abstract: In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.
    Type: Application
    Filed: July 19, 2004
    Publication date: December 23, 2004
    Inventors: Makoto Oikawa, Hiroki Etou, Hirotoshi Kubo, Shouji Miyahara
  • Patent number: 6828626
    Abstract: In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: December 7, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Makoto Oikawa, Hiroki Etou, Hirotoshi Kubo, Shouji Miyahara
  • Publication number: 20030080379
    Abstract: In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.
    Type: Application
    Filed: September 25, 2002
    Publication date: May 1, 2003
    Inventors: Makoto Oikawa, Hiroki Etou, Hirotoshi Kubo, Shouji Miyahara
  • Patent number: 6545364
    Abstract: After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: April 8, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi, Hirokazu Fukuda, Hiroki Etou
  • Publication number: 20020053744
    Abstract: A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.
    Type: Application
    Filed: March 16, 2001
    Publication date: May 9, 2002
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Hirokazu Fukuda, Hiroki Etou, Kouji Takahashi
  • Publication number: 20020027276
    Abstract: After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.
    Type: Application
    Filed: March 16, 2001
    Publication date: March 7, 2002
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi, Hirokazu Fukuda, Hiroki Etou
  • Patent number: 5915179
    Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: June 22, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroki Etou, Kazunori Ohno, Takaaki Saito, Naofumi Tsuchiya, Toshinari Utsumi