Abstract: A microprocessor which can be operated with small power consumption, a microprocessor designing program which can design it in a short period of time, and a microprocessor designing apparatus. The microprocessor designing program comprises an execution program storing step of storing each of the execution programs in said specified address areas, in correspondence with the specification of said address areas made for each of the execution programs, an access number totalizing step of counting a total number of accesses given by the computation processing unit for each of the address areas, and an execution program name outputting step of outputting an execution program name outputted in an order based on said total number. The microprocessor designing apparatus packages a microprocessor designing program, and comprises an execution program name displaying component displaying, in characters, the name of an execution program outputted by the execution program name displaying step.

Abstract: A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program counter. The access control unit controls the transfer of the program code according to the values of both the address counter and the program counter, thereby enabling the computational unit to start executing the program code before the entire program has been transferred. Program initialization can therefore be completed quickly, and the program can promptly begin producing audible or visible results.

Abstract: Halting clocks of pipeline registers 28-31 and data memory 26, etc., and holding input data of each of FE, DC, MEM, WB stages, during when a nop is sent to each of pipelines, by a first process for outputting a nop signal S41 of logic level “H” when the nop is detected by a nop detecting circuit 41, a second process for sending the detected nop signal to each of the pipelines by F/Fs 46-48 placed between each of the pipelines, and a third process for halting clocks by clock control circuits 42-45 placed in each of the pipelines when the nop signal is sent to each of the pipelines.

Abstract: An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more functional blocks; carrying out logic composition with respect to the functional elements decided by the functional design using the timing model of the functional blocks under the first mode; performing a first timing analysis with respect to the functional elements on which logic composition was carried out using the timing model under the first mode; performing layout based on the result of the logic composition and the first timing analysis; and performing a second timing analysis after the layout using the timing model under the second mode.

Abstract: A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

Abstract: The present invention provides a camera data transfer system comprising an imaging means for generating image data and outputting the same, and a camera interface means including a first holding means for holding one frame-preceding image data, a second holding means for holding the present image data, a comparing means for comparing the contents of the first and second holding means, and a bus interface means for controlling the input/output of data to and from a bus. In the camera data transfer system, the data is transferred to a frame memory of a display means connected to the bus through the bus interface means to cause the frame memory to display the data thereon.

Abstract: A dual port RAM includes an any-time readable/writable memory block in which an access can be made to the same storage area from independent first and second ports. In addition, the RAM includes a first test circuit for performing a test to the storage area of the memory block via the first port on the basis of a first clock signal, and a second test circuit for performing a test to the storage area of the memory block via the second port on the basis of a second clock signal. A control circuit of the RAM causes the first and second test circuits to test the memory block in an alternating manner.

Abstract: An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more functional blocks; carrying out logic composition with respect to the functional elements decided by the functional design using the timing model of the functional blocks under the first mode; performing a first timing analysis with respect to the functional elements on which logic composition was carried out using the timing model under the first mode; performing layout based on the result of the logic composition and the first timing analysis; and performing a second timing analysis after the layout using the timing model under the second mode.

Abstract: A digital signal processor includes a programmable memory, a processor and an access controller. The programmable memory has blocks each of which is capable of reading and writing an instruction of a program. The processor sequentially executes the instruction stored in the programmable memory. The access controller sequentially stores the instruction of the program in the blocks of the programmable memory on the basis of an address indicating a location of the respective blocks where the instruction is stored. The access controller controls an access of the processor to the respective blocks.

Abstract: The present invention provides a LSI being capable of testing a signal path between two circuit blocks by a scan isolation test. A scan isolation circuit 30-1 includes a first selector 31 alternating a held signal S33 or a signal SA from circuit block 10A and outputting the alternated signal thereof as signals 31, and a second selector 32 selecting the signal S31 or one signal from the signal SAm from outside or the previous-stage signal S33. Further, the held signal S33 held in the FF 33 thereof is supplied to the selector 31 and the next-stage scan isolation circuit 30-2, connecting the FF 33 to the output terminal. During the test therein, since the signal SA is held through the selectors 31 and 32, the signal path between the circuit blocks 10A and 10B can be conducted.

Abstract: The present invention provides an apparatus for designing a semiconductor integrated circuit, which is capable of satisfying timing constraints without providing BFBs, and improving a convergent property at optimization, and a design method therefor. An LSI automatic design simulator (10) determines the number of clocks employed in a clock generating functional part (30) and delays in respective clocks, allocates the clocks set as clock systems, and verifies constraint conditions with respect to design, based on the respective clocks. A tree determining functional part (32) adjusts skews of the respective clocks through the use of the produced cock systems, makes delay adjustments to the clocks, verifies a layout adjustment, and fetches therein data supplied thereto without timing constraint violation, thereby making it possible to further enhance a convergent property that satisfies all of timing constraints.

Abstract: A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program counter. The access control unit controls the transfer of the program code according to the values of both the address counter and the program counter, thereby enabling the computational unit to start executing the program code before the entire program has been transferred. Program initialization can therefore be completed quickly, and the program can promptly begin producing audible or visible results.

Abstract: A semiconductor integrated circuit includes first and second data paths, first to third flip flops and logic circuits. The first data path transfers input data. The first flip flop is coupled to the first data path for temporally storing data received from the first data path in response to a first clock signal that is delayed from a reference clock signal. One of the logic circuits receives data from the first flip flop and another logic circuit outputs output data. The second flip flop is connected between the logic circuits for transferring signal between them in response to the reference clock signal. The third flip flop is connected to another logic circuit for outputting the output data in response to a second clock signal that is advanced from the reference clock signal. The second data path transfers data received from the third flip flop.

Abstract: A digital signal processor includes a programmable memory, a processor and an access controller. The programmable memory has blocks each of which is capable of reading and writing an instruction of a program. The processor sequentially executes the instruction stored in the programmable memory. The access controller sequentially stores the instruction of the program in the blocks of the programmable memory on the basis of an address indicating a location of the respective blocks where the instruction is stored. The access controller controls an access of the processor to the respective blocks.

Abstract: A semiconductor integrated circuit includes logic circuits, each of which receives an input signal and generates an output signal having bits, and a selector which is coupled to the logic circuits and selectively transfers either one of the output signals output from the logic circuits in response to a selection signal. The semiconductor integrated circuit also includes a comparator which compares the output signals output from the logic circuits with an expected value signal and outputs a result of the comparison, and output terminals. The semiconductor integrated circuit also includes an output buffer which is coupled between the selector and the output terminals, and which controls transferring the output signal transferred from the selector to the output terminals in response to the result of the comparison.

Abstract: A dual port RAM includes an any-time readable/writable memory block in which an access can be made to the same storage area from independent first and second ports. In addition, the RAM includes a first test circuit for performing a test to the storage area of the memory block via the first port on the basis of a first clock signal, and a second test circuit for performing a test to the storage area of the memory block via the second port on the basis of a second clock signal. A control circuit of the RAM causes the first and second test circuits to test the memory block in an alternating manner.