Patents by Inventor Hiroki HATADA

Hiroki HATADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12660287
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third semiconductor regions and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer. An upper part of the gate electrode includes first and second electrode portions. The first electrode portion faces the third semiconductor region via the gate insulating layer. The second electrode portion is arranged with the first electrode portion. The second electrode is located on the second and third semiconductor regions. The third electrode includes an interconnect part located on the second electrode portion and is separated from the second electrode.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: June 16, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroki Hatada
  • Patent number: 12550349
    Abstract: A semiconductor device according to an embodiment includes: a first semiconductor region of a first conductivity type disposed; a second semiconductor region of a second conductivity type disposed on the first region; a third semiconductor region of the first conductivity type disposed on the second region; an insulating film disposed in the first, second and third regions; and a second electrode disposed in the insulating film so as to be adjacent to the second region via the insulating film. The second region includes a boundary region that is in contact with the insulating film and faces the second electrode, the boundary region includes a high-concentration region, the insulating film includes a first region in contact with the high-concentration region and a second region in contact with a low-concentration region, and a thickness of the second region is smaller than a thickness of the first region.
    Type: Grant
    Filed: August 15, 2023
    Date of Patent: February 10, 2026
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroki Hatada
  • Publication number: 20250280587
    Abstract: A semiconductor device includes: a second electrode, located in a semiconductor part, extending in a first direction; a third electrode, located in the semiconductor part, including a first portion, a second portion, and a first middle portion positioned below the second electrode between the first portion and the second portion, the second electrode being located between the first portion and the second portion in the first direction; a fourth electrode, located above the semiconductor part, including a pad portion separated from the second electrode and the second portion in a second direction, and a protrusion protruding from the pad portion and covering the second electrode and being connected to the second electrode; and a fifth electrode, located above the semiconductor part, including a first covering portion being connected to the first contact portion and a second covering portion being connected to the first portion.
    Type: Application
    Filed: March 18, 2025
    Publication date: September 4, 2025
    Inventors: Hiroki HATADA, Kohei OASA
  • Patent number: 12283615
    Abstract: A semiconductor device includes: a second electrode, located in a semiconductor part, extending in a first direction; a third electrode, located in the semiconductor part, including a first portion, a second portion, and a first middle portion positioned below the second electrode between the first portion and the second portion, the second electrode being located between the first portion and the second portion in the first direction; a fourth electrode, located above the semiconductor part, including a pad portion separated from the second electrode and the second portion in a second direction, and a protrusion protruding from the pad portion and covering the second electrode and being connected to the second electrode; and a fifth electrode, located above the semiconductor part, including a first covering portion being connected to the first contact portion and a second covering portion being connected to the first portion.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: April 22, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroki Hatada, Kohei Oasa
  • Publication number: 20250081577
    Abstract: A semiconductor device of embodiments includes: a semiconductor layer including a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, and a third semiconductor region of the first conductive type; and a gate electrode. The second semiconductor region includes first, second, and third regions. The gate electrode includes first, second, and third portions. The first, second, and third portions face the first, second, and third regions, respectively. The first portion, the second portion, and the third portion contain a first material, a second material, and a third material, respectively. When the first conductive type is n-type, the work function of the first material and the third material are smaller than that of the second material. When the first conductive type is p-type, the work function of the first material and the third material are larger than that of the second material.
    Type: Application
    Filed: February 28, 2024
    Publication date: March 6, 2025
    Inventors: Masatsugu NAGAI, Hiroki HATADA
  • Publication number: 20250081548
    Abstract: A semiconductor device includes first and second electrodes, first to third semiconductor regions, a structure body, and first and second connection parts. The structure body includes an insulating part, and third and fourth electrodes. A shape of the structure body in a plane is a first hexagon. The first hexagon includes a pair of first sides, a pair of second sides, and a pair of third sides. A length of the pair of first sides is greater than a length of the pair of second sides. The fourth electrode includes a pair of first electrode regions, a pair of second electrode regions, and a pair of third electrode regions. The second connection part is located on the pair of first electrode regions.
    Type: Application
    Filed: March 5, 2024
    Publication date: March 6, 2025
    Inventors: Hiroki HATADA, Tsuyoshi KACHI
  • Publication number: 20240313093
    Abstract: A semiconductor device according to an embodiment includes: a first semiconductor region of a first conductivity type disposed; a second semiconductor region of a second conductivity type disposed on the first region; a third semiconductor region of the first conductivity type disposed on the second region; an insulating film disposed in the first, second and third regions; and a second electrode disposed in the insulating film so as to be adjacent to the second region via the insulating film. The second region includes a boundary region that is in contact with the insulating film and faces the second electrode, the boundary region includes a high-concentration region, the insulating film includes a first region in contact with the high-concentration region and a second region in contact with a low-concentration region, and a thickness of the second region is smaller than a thickness of the first region.
    Type: Application
    Filed: August 15, 2023
    Publication date: September 19, 2024
    Inventor: Hiroki HATADA
  • Publication number: 20240088250
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third semiconductor regions and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The gate electrode faces the second semiconductor region via a gate insulating layer. An upper part of the gate electrode includes first and second electrode portions. The first electrode portion faces the third semiconductor region via the gate insulating layer. The second electrode portion is arranged with the first electrode portion. The second electrode is located on the second and third semiconductor regions. The third electrode includes an interconnect part located on the second electrode portion and is separated from the second electrode.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 14, 2024
    Inventor: Hiroki HATADA
  • Publication number: 20230085094
    Abstract: A semiconductor device includes: a second electrode, located in a semiconductor part, extending in a first direction; a third electrode, located in the semiconductor part, including a first portion, a second portion, and a first middle portion positioned below the second electrode between the first portion and the second portion, the second electrode being located between the first portion and the second portion in the first direction; a fourth electrode, located above the semiconductor part, including a pad portion separated from the second electrode and the second portion in a second direction, and a protrusion protruding from the pad portion and covering the second electrode and being connected to the second electrode; and a fifth electrode, located above the semiconductor part, including a first covering portion being connected to the first contact portion and a second covering portion being connected to the first portion.
    Type: Application
    Filed: February 10, 2022
    Publication date: March 16, 2023
    Inventors: Hiroki HATADA, Kohei OASA