Patents by Inventor Hiroki Hiramatsu

Hiroki Hiramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089344
    Abstract: A transmitting terminal can transmit a content held by itself to a specific receiving terminal having no email software as if using a mailer. The transmitting terminal (10) and the receiving terminal (20) are connected to a delivery server (30) via a network (4). The delivery server (30) comprises: a database (36) for registering the device ID that specifies the receiving terminal (20); a content storage (39) for temporarily storing a content transmitted from the transmitting terminal (10); and table (33, 37) for managing contents separately on a per device ID basis of the receiving terminal. The delivery server (30), when receiving a request from the receiving terminal (20), refers to the tables (33, 27) and transmits to the receiving terminal (20) a content, the transmission destination of which corresponds to the device ID of the receiving terminal (20).
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Hiroki Mizosoe, Junji Shiokawa, Kazuto Yoneyama, Kunihiro Nomura, Masaaki Hiramatsu, Yasuhisa Mori, Takashi Yoshimaru, Kazuaki Aoyama, Tomomu Ishikawa, Yo Miyamoto
  • Patent number: 8987859
    Abstract: Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Pavel S. Plekhanov, Kevin J. Fischer, Qiang Fu, Hiroki Hiramatsu
  • Publication number: 20140151889
    Abstract: Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material.
    Type: Application
    Filed: December 4, 2012
    Publication date: June 5, 2014
    Inventors: Pavel S. Plekhanov, Kevin J. Fischer, Qiang Fu, Hiroki Hiramatsu