Abstract: Apparatuses and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer including a portion; a second conductive layer: a contact coupled to the portion of the first conductive layer; a third conductive layer between the first conductive layer and the second conductive layer, coupled to the contact; one or more capacitor elements wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

Abstract: A wafer inspection apparatus according to one embodiment is a wafer inspection apparatus including a plurality of inspection parts arranged in a height direction and a lateral direction, and includes a pair of air circulating means disposed at both ends in a longitudinal direction of an air circulating region including the plurality of inspection parts arranged in the lateral direction and configured to circulate air in the circulating region.

Abstract: An inspection apparatus includes a load port area in which a carrier accommodation chamber for accommodating a carrier that receives an inspection object is disposed; an inspection area in which a plurality of probe cards are respectively disposed under a plurality of inspection devices, and in which the probe card is pressed against an electronic device of the inspection object on a chuck top to inspect the electronic device; a transfer area in which a transfer mechanism transfers the inspection object onto the chuck top; and a plurality of probe card accommodation devices disposed in at least one of the load port area or the inspection area, each probe card accommodation device being capable of accommodating the probe card, and a number of the probe card accommodation devices being equal to or greater than a number of the probe cards.

Abstract: Apparatuses and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer including a portion; a second conductive layer: a contact coupled to the portion of the first conductive layer; a third conductive layer between the first conductive layer and the second conductive layer, coupled to the contact; one or more capacitor elements wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.

Abstract: Techniques for testing both a rectangular substrate and a circular substrate are provided. One aspect of the present disclosure pertains to a test device comprising an exchangeable change kit, wherein the change kit comprises a first holding device and a second holding device which are exchangeably mounted in the test device, wherein the first holding device is configured to adsorb and hold a rectangular substrate, wherein the second holding device is configured to adsorb and hold a circular substrate, and wherein the first holding device and the second holding device are exchanged according to a substrate to be tested.

Abstract: Memory devices are disclosed. A memory device may include a first row of power supply pads and a first row of input/output (DQ) pads. The memory device may further include a row of vias, wherein the first row of DQ pads is positioned at least partially between the row of vias and the first row of power supply pads. The memory device may also include a number of conductors, wherein each via of the row of vias is coupled, via an associated conductor of the number of conductors, to either a power supply pad of the first row of power supply pads or a DQ pad of the first row of DQ pads. Methods of forming an interface region of a memory device, and electronic systems are also disclosed.

Abstract: An inspection apparatus includes a load port area in which a carrier accommodation chamber for accommodating a. carrier that receives an inspection object is disposed; an inspection area in which a plurality of probe cards are respectively disposed under a plurality of inspection devices, and in which the probe card is pressed against an electronic device of the inspection object on a chuck top to inspect the electronic device; a transfer area in which a transfer mechanism transfers the inspection object onto the chuck top; and a plurality of probe card accommodation devices disposed in at least one of the load port area or the inspection area, each probe card accommodation device being capable of accommodating the probe card, and a number of the probe card accommodation devices being equal to or greater than a number of the probe cards.

Abstract: Some embodiments include an integrated assembly having a capacitive unit which includes a plurality of capacitive subunits. A first conductive structure is under a first group of the capacitive subunits and is coupled with them. A second conductive structure is under a second group of the capacitive subunits and is coupled with them. A third conductive structure is over the capacitive subunits and is coupled with all of the capacitive subunits. A resistive structure extends under the first and second conductive structures. The resistive structure has a first-end-region under the first conductive structure and coupled with the first conductive structure. The resistive structure includes resistive lines extending from the first-end-region to second-end-regions.

Abstract: Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.

Abstract: Some embodiments include an integrated assembly having a capacitive unit which includes a plurality of capacitive subunits. A first conductive structure is under a first group of the capacitive subunits and is coupled with them. A second conductive structure is under a second group of the capacitive subunits and is coupled with them. A third conductive structure is over the capacitive subunits and is coupled with all of the capacitive subunits. A resistive structure extends under the first and second conductive structures. The resistive structure has a first-end-region under the first conductive structure and coupled with the first conductive structure. The resistive structure includes resistive lines extending from the first-end-region to second-end-regions.

Abstract: A wafer inspection apparatus according to one embodiment is a wafer inspection apparatus including a plurality of inspection parts arranged in a height direction and a lateral direction, and includes a pair of air circulating means disposed at both ends in a longitudinal direction of an air circulating region including the plurality of inspection parts arranged in the lateral direction and configured to circulate air in the circulating region.

Abstract: Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.

Abstract: Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.

Abstract: In a transfer method for transferring a substrate in an inspection system configured to perform a test on electrical characteristics of the substrate, the inspection system including an inspection unit including a plurality of test devices configured to perform the test on the electrical characteristics of a substrate, a loader unit configured to mount a cassette which accommodates a plurality of substrates, and a transfer device configured to transfer a substrate between the inspection unit and the loader unit, an inspected substrate is received by the transfer device from the inspection unit. The inspected substrate received from the inspection unit is transferred toward the loader unit in a state where an opening portion of a transfer arm container of the transfer device. Then, the inspected substrate is delivered to the loader unit.

Abstract: In a transfer method for transferring a substrate in an inspection system configured to perform a test on electrical characteristics of the substrate, the inspection system including an inspection unit including a plurality of test devices configured to perform the test on the electrical characteristics of a substrate, a loader unit configured to mount a cassette which accommodates a plurality of substrates, and a transfer device configured to transfer a substrate between the inspection unit and the loader unit, an inspected substrate is received by the transfer device from the inspection unit. The inspected substrate received from the inspection unit is transferred toward the loader unit in a state where an opening portion of a transfer arm container of the transfer device. Then, the inspected substrate is delivered to the loader unit.

Abstract: A wafer transfer device includes: a wafer compartment; a pre-alignment chamber, provided either above or below the wafer compartment; a first wafer transfer chamber, provided in a vertical direction along the wafer compartment and the pre-alignment chamber, for transferring the semiconductor wafer from the wafer compartment to the pre-alignment chamber; and an alignment chamber for aligning the semiconductor wafer, the alignment chamber being provided adjacent to the pre-alignment chamber. The wafer transfer device further includes a second wafer transfer chamber, disposed along an arrangement direction of the first wafer transfer chamber, the pre-alignment chamber and the alignment chamber, for transferring the semiconductor wafer among the pre-alignment chamber, the alignment chamber and the test chambers.